Controlling flash memory program and erase pulses

Details Controlling flash memory program and erase pulses Controlling flash memory program and erase pulses

1997-06-19

1999-05-25

Heckler, Thomas M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711170, G06F 114, G11C 1602

Patent

active

059077000

ABSTRACT:
An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal from the blocking circuit during each sub-step until a final sub-step. For one embodiment, the operation to be performed is an erase operation specified by a write state machine that specifies an erase block to be erased within a flash memory. Alternately, the operation to be performed is a program operation specified by a write state machine that specifies data to be programmed within a flash memory.

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Japanese translation (2 pgs.)-Foreign Counterpart to U.S. Application Serial No. 07/969,131.
Co-pending patent application entitled, "Improved Method and Apparatus for Sequential Programming of a Flash EEFROM Memory Array" U.S. Serial No.: 08/252,850; Filed: Jun. 2, 1994.
Co-pending patent application entitled, "Method and Apparatus for Programming and Erasing Flash EEPROM Memory Arrays Utilizing a Charge Pump Circuit" U.S. Serial NO.: 08/119,423; Filed: Sep. 10, 1993.
Co-pending patent application entitled, "Zeros Detector for Limited Programming of a Flash Memory", U.S. Serial No.: 08/325,874; Filed: Oct. 19, 1994.
Co-pending patent application entitled, "A Low Current Reduced Area Programming Voltage Detector for Flash Memory" U.S. Serial No.: 08/326,668; Filed: Oct. 19, 1994.
Co-pending patent application entitled, "Flash Memory Array System and Method" U.S. Serial No.: 08/086,186; Filed: Jun. 30, 1993.
Co-pending patent application entitled, "A Low Power Voltage Detector Circuit Including a Flash Memory Cell" U.S. Serial No.: 08/326,689; Filed: Oct. 19, 1994.
Co-pending patent application entitled, "A Charge Pump Circuit for Providing Multiple Output Voltage for Flash Memory" U.S. Serial No.: 08/326,654; Filed: Oct. 19, 1994.
Co-pending patent application entitled, "Method and Apparatus for Detecting and Selecting Voltage Supplied for Flash Memory" U.S. Serial No.: 08/326,702; Filed: Oct. 19, 1994.
Co-pending patent application entitled, "A Low Power Pulse Generator for Smart Voltage Flash EEPROM" U.S. Serial No.: 08/326,703; Filed Oct. 19, 1994.

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