Controlling contention via transactional timers among...

Details Controlling contention via transactional timers among... Controlling contention via transactional timers among...

2005-04-18

2009-02-24

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S151000, C711S152000, C711S147000, C711S130000, C711S144000, C711S145000, C711S119000

Reexamination Certificate

active

07496726

ABSTRACT:
A system for controlling contention between conflicting transactions in a transactional memory system. During operation, the system receives a request to access a cache line and then determines if the cache line is already in use by an existing transaction in a cache state that is incompatible with the request. If so, the system determines if the request is from a processor which is in a polite mode. If this is true, the system denies the request to access the cache line and continues executing the existing transaction.

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