Controlling an I/O MMU

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S154000, C711S203000, C711S205000, C711S206000, C711S207000, C710S005000, C710S036000, C710S039000

Reexamination Certificate

active

07543131

ABSTRACT:
In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configured to implement address translation and memory protection for memory operations sourced by one or more input/output (I/O) devices. The memory stores a command queue during use. The memory management module is configured to write one or more control commands to the command queue, and the IOMMU is configured to read the control commands from the command queue and execute the control commands.

REFERENCES:
patent: 3970999 (1976-07-01), Edward
patent: 4550368 (1985-10-01), Bechtolsheim
patent: 5301287 (1994-04-01), Herrell et al.
patent: 5317710 (1994-05-01), Ara et al.
patent: 5949436 (1999-09-01), Horan et al.
patent: 5987557 (1999-11-01), Ebrahim
patent: 6065088 (2000-05-01), Bronson et al.
patent: 6119204 (2000-09-01), Chang et al.
patent: 6622193 (2003-09-01), Avery
patent: 6886171 (2005-04-01), MacLeod
patent: 6888843 (2005-05-01), Keller et al.
patent: 6901474 (2005-05-01), Lym et al.
patent: 6928529 (2005-08-01), Shinomiya
patent: 6938094 (2005-08-01), Keller et al.
patent: 7073043 (2006-07-01), Arimilli et al.
patent: 7190694 (2007-03-01), Sato et al.
patent: 2002/0083254 (2002-06-01), Hummel et al.
patent: 2006/0075146 (2006-04-01), Schoinas et al.
patent: 2006/0277348 (2006-12-01), Wooten
U.S. Appl. No. 11/503,391, entitled “Avoiding silent data corruption and data leakage in a virtual environment with multiple guests”.
U.S. Appl. No. 11/503,375, entitled “Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)”.
Motorola, “PowerPC 601 RISC Microprocessor User's Manual,” 1993, Chapter 6 “Memory Management Unit,” International Business Machines Corporation.
AMD, “AMD x86-64 Architecture Programmer's Manual,”Sep. 2002, Chapter 5, “Page Translation and Protection,” pp. 143-176.
Office Action from U.S. Appl. No. 11/503,391 mailed Sep. 18, 2008.
Response to Office Action from U.S. Appl. No. 11/503,391 filed Dec. 11, 2008.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Controlling an I/O MMU does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Controlling an I/O MMU, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Controlling an I/O MMU will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4114226

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.