Controlling an accumulation of timing errors in a...

Details Controlling an accumulation of timing errors in a... Controlling an accumulation of timing errors in a...

2006-02-14

2008-12-09

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C327S292000, C375S371000, C713S400000

Reexamination Certificate

active

07464285

ABSTRACT:
Apparatus (100) for communicating clock correction data between two or more clocked entities (102, 104) using a standardized clock correction unit or quanta. A source-native pre-scaler (302) can convert source-native clock correction values to scaled source-native clock correction values. The pre-scaler can perform this conversion by multiplying each source-native clock correction value by a factor N1. A source-native divider (308) can divide an adjusted source-native clock correction value by a value M1to produce a standard quotient and a standard remainder. The standard quotient defines a standard clock correction value. Further, a source-native accumulator306can accumulate a sum comprised of the scaled source-native clock corrections and the standard remainder produced from the source-native divider. The sum can define the adjusted source-native clock correction value.

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