Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
2008-05-13
2008-05-13
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Reexamination Certificate
active
07373487
ABSTRACT:
A master CPU and a slave CPU for processing data supplied from a detector unit, and a timer cleared by a clear signal supplied every predetermined time period from the master CPU when the operation of the master CPU is normal and adapted for supplying a reset signal to the master CPU and the slave CPU after the lapse of the predetermined time period and further after the lapse of another predetermined time period when an anomaly occurs in the operation of the master CPU. The master CPU monitors the processing data outputted from the slave CPU, and supplies a forced reset signal to the slave CPU when anomaly in the operation of the slave CPU is detected.
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European Search Report for corresponding European Patent Application Serial No. 03007913.1-1225 dated Aug. 16, 2007.
Kato Hironori
Sanpei Yoshio
Alps Electric Co. Ltd
Brinks Hofer Gilson & Lione
Coleman Eric
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