Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1998-12-18
2001-03-20
Lee, Thomas (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S020000, C710S022000, C710S024000, C710S072000, C710S074000, C710S262000
Reexamination Certificate
active
06205494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to storage target controllers which respond to commands from initiators. More particularly, the invention relates to hardware assistance in a storage target controller for optimizing command processing, thereby improving performance.
2. Description of the Prior Art and Related Information
Each device connected to a SCSI bus is classified as either an initiator or a target. An initiator originates an operation and is usually a host computer. A target device performs the operation and is usually a peripheral device controller directed by a microprocessor. One example of a target device is a disk drive. There can be multiple initiators and targets on a SCSI bus.
A disk drive target controller receives commands to read or write data from an initiator, such as a host computer. The disk controller typically comprises a microprocessor for interpreting the commands, setting up disk operations resulting from the commands, and managing a buffer to cache data transferred to and from the disk. An ASIC (application specific integrated circuit) is connected to the microprocessor to provide an interface to the SCSI bus and alert the microprocessor with priority interrupts when commands are received from the host. The performance of a target disk controller depends in part on the time required by the microprocessor to interpret, set up, and execute the commands, sometimes termed command overhead. For commands specifying long data transfers, the command overhead is amortized over relatively long periods and is less significant. When data transfers specified by each command are relatively short, the command overhead becomes a significant performance factor.
A target disk controller receives a SCSI command from the host initiator in the form of a six, ten or twelve byte command descriptor block (CDB).
FIG. 1
illustrates a 6-byte (numbered byte 0-5) CDB
100
, representative of the type of information conveyed in the command. Byte 0, the first byte, has two segments—a group code
102
and a command code
104
. The group code
102
implies the number of bytes in the CDB, while the command code
104
specifies an operation such as Read or Write. Byte 1 comprises a three-bit logical unit number (LUN)
106
which addresses up to eight logical entities within the target and a five-bit field
108
A which contains the most significant bits of a logical block address (LBA), the indivisible addressable unit in the target. Disk drives conventionally have one LUN and the host views and references data in the drive as a sequence of LBAs ranging from 0 to the maximum capacity of the drive. Each LBA represents a block of data which is a fixed length, conventionally 512 bytes although other block sizes can be defined. The logical block address continues in bytes 2 and 3 providing segments
108
B and
108
C. Collectively
108
A-C provide the starting LBA for the current command.
Byte 4 varies depending on the command to be executed. For read and write commands which transfer data, the byte is a transfer length field
110
providing the number of data blocks to be transferred. Alternately for other types of commands, byte 4 may contain a parameter list length field
112
or an allocation length field
114
. CDBs of 10 and 12 bytes in length provide larger fields for logical block addresses. CDB byte 5 is a control byte
116
and may contain vendor-specific information and flags. Conventionally, a microprocessor in the target controller receives the CDB
100
and schedules execution of disk activity according to the requirements in the command.
FIG. 2
shows the format of a queue tag message which may be received by the target from a host initiator. Tagged queuing allows a target to accept multiple I/O processes from a single initiator and intelligently choose which command to perform. A 2-byte queue tag message
200
is sent by the initiator following connection to the target and prior to sending a read or write CDB
100
.
The first byte of the queue tag message
200
contains a message code
202
indicating the order in which the target may schedule the command for execution. Simple queue tag (20h) message code indicates that the command may be executed in any order desired, based on the target's command queue management algorithm. Ordered queue tag (22h) message code directs the target to execute the command in the order received with respect to other ordered queue tag messages received. All commands with simple queue tag messages received prior to a command with an ordered queue tag message are executed before the command received with the ordered queue tag message. All commands with simple queue tag messages received after commands with an ordered queue tag message are executed after the command received with the ordered queue tag message. Head of queue (21h) message code
202
directs the target to place the command first in the queue so as to be executed next. A command with a head of queue message code is executed prior to any queued I/O process. The second message byte
204
contains a queue tag which uniquely identifies the I/O process requested.
Frequently, a series of commands is received by the target which specifies contiguous chains of LBAs. These commands are termed “sequential” and the target microprocessor is able to recognize the sequentiality and improve the efficiency of disk operations and host data transfer as a result. Despite the improvement from recognizing sequentiality, the performance of the system suffers from the time required for the microprocessor to process each command, termed command overhead, including interrupting the microprocessor for each command received and executing code to process the command. This is particularly true when a series of sequential commands specify relatively short chains of LBAs so that the ratio of command overhead to command execution is high.
FIG. 3
shows an example of prior art processing of a group
300
of four sequential read CDBs
305
,
310
,
315
,
320
received by a target. For each CDB in the group
300
, an interrupt
350
of the target microprocessor is requested. The target microprocessor responds to the priority interrupt
350
, parses the command to determine requirements and schedules (queues) future execution of disk operations and host transfers
360
for the command. As each disk and host transfer operation completes, status
380
is sent to the initiator. The sequence of
FIG. 3
is valid for a series of read commands. In the event of a series of write commands, the host interface must be programmed by the microprocessor to send status after the data has been written to the disk. An interrupt is requested after the status is sent to inform the microprocessor that the host has received completion status for the command. Returning to the read command case, in the course of processing the commands after each interrupt
350
, the target microprocessor is able to recognize the sequential nature of commands
305
,
310
,
315
, and
320
and may advantageously cause the data for all four commands to be read during one revolution of the disk, providing that the commands are received and queued in time.
Particularly when performing a series of relatively short length read or write commands, the command overhead resulting from interrupts is a significant percentage of the overall time required to execute each command thus reducing the performance of the disk drive. A need therefore exists to provide a performance improvement by reducing command overhead.
SUMMARY OF THE INVENTION
This invention can be regarded as a target interface controller for connecting a target to an initiator over a communication bus. The target interface controller comprises: a host interface means, for connecting to the communication bus and for communicating between the target and the initiator; an interface microprocessor; a bus interface means for connecting to the interface microprocessor; a command queuing means, connected to the bus interface means and separated from the interface
Lee Thomas
Nguyen Tanh
Shara Milad G
Western Digital Corporation
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