Controller that supports data merging utilizing a slice addressa

Details Controller that supports data merging utilizing a slice addressa Controller that supports data merging utilizing a slice addressa

1998-01-26

2000-10-17

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711104, 711154, 711169, 711201, 707101, G06F 1202

Patent

active

061346322

ABSTRACT:
A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line. Also provided is a method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory-write operation. The method includes setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to slices of a word line associated with the set slice enable bits in the slice-addressable random access memory buffer; and write-merging data from the modified cache line to slices of the word line not associated with the set slice-enable bits in the slice-addressable random access memory buffer.

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