Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-31
2001-02-20
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S018000, C700S018000
Reexamination Certificate
active
06192506
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an apparatus for solving logic and, more particularly, to a controller for solving boolean logic.
2. Background Information
Programmable logic controllers (PLCs) are well-known in the art. PLCs are utilized in a wide variety of industrial plants to solve ladder logic, such as a ladder diagram, which is represented by a power rail, plural input contacts, one or more output coils and a neutral rail. Typically, PLCs employ a combination of hardware and/or software circuits to rapidly solve the ladder logic.
Although ladder logic is readily understood by plant personnel responsible for the operation of an industrial plant, often, the control strategy, as designed by control engineers, is defined using standard graphic symbols. For example, when the control strategy includes boolean logic, circuit elements such as AND, OR and NOT logic gates are employed. Accordingly, whenever that control strategy is implemented in PLCs or other controllers for the plant control system, it is necessary to convert the control strategy from boolean logic to ladder logic.
It is known to solve either ladder logic or boolean logic in software. For example, a processor employs “hot code” which is pre-compiled to solve a particular set of ladder logic or boolean logic, respectively. Whenever changes to the ladder logic or boolean logic are required, it is necessary to recompile the “hot code” for the different logic configuration. Another disadvantage of “hot code” is that each of the respective ladder logic elements or boolean logic elements must be fully evaluated to determine the final logic outputs.
It is also known to monitor all inputs to the ladder logic or boolean logic for any change of state. Whenever a change of one or more inputs is detected, the corresponding logic is evaluated to determine the new results. Under normal conditions, during which only a relatively few inputs change over a relatively long period of time, there is no problem. However, under plant upset conditions (e.g., the trip of a power plant), many inputs may change in relatively short succession, thereby possibly overloading the control system.
Accordingly, there is room for improvement.
SUMMARY OF THE INVENTION
The present invention provides a controller which solves logic. The logic includes a logic function having a target value and a plurality of inputs. As an important aspect of the invention, the controller includes means for solving the logic function when the value of any of its inputs is equal to its target value. In this manner, typically, only a portion of the overall logic function needs to be solved, thereby improving the performance of the controller.
The controller comprises means for storing representations of logic which includes a logic function having a target value and a plurality of inputs each of which has a value; means for providing a plurality of digital logic signals; means for solving the representations of the logic employing at least some of the digital logic signals; and means for solving the logic function when the value of any of the inputs is equal to the target value.
As a preferred refinement, the logic includes a plurality of logic circuit elements. The means for solving the logic function, which has an execution cycle during which the logic function is solved, includes means for solving the boolean value of one of the logic circuit elements and for solving the boolean value of the other logic circuit elements. This latter means solves the boolean value of the one logic circuit element once during the execution cycle. As the output of the one logic circuit element may be input by other logic circuit elements, this further improves the performance of the controller.
As another preferred refinement, the means for storing representations of logic includes first memory means for storing first boolean values, and the means for providing a plurality of digital logic signals includes second memory means for storing second boolean values. The inputs of the logic circuit elements include at least one first input which is connected to the output of one of the logic circuit elements, and at least one second input having one of the second boolean values. The means for solving the logic function includes output solving means for solving the output of the latter logic circuit element and storing the same as one of the first boolean values.
As a further refinement, the means for solving the logic function further includes logic solving means for solving the logic when either: (a) either the latter first boolean value or the latter second boolean value is equal to the target value, or (b) all of the logic circuit elements of the logic have been solved. Since, typically, only a portion of the logic circuit elements needs to be solved, this enhances performance.
As another refinement, the means for providing a plurality of digital logic signals includes memory means for storing boolean values. The at least one input of the logic circuit elements is a plurality of first inputs each of which is interconnected with the output of one of the logic circuit elements, and a plurality of second inputs each of which has one of the boolean values stored by the memory means. The means for solving the logic function has an execution cycle during which the logic function is solved and includes means for determining in a current execution cycle whether the target value of one of the second inputs is equal to the latter boolean value stored by the memory means by evaluating one of the second inputs, and means for evaluating in a subsequent execution cycle the second inputs to determine whether the latter target value is equal to the latter boolean value before evaluating the first inputs. In this manner, additional optimization is applied during execution by dynamically scheduling the order of evaluation of the first inputs and the second inputs.
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patent: 5265004 (1993-11-01), Schultz
patent: 5623401 (1997-04-01), Baxter
patent: 5731712 (1998-03-01), Welch
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patent: 6021357 (2000-02-01), Peterson
Edblad Warren A.
Kephart, Jr. Richard W.
Spillane Donal A.
Vishnubhatla Suresh K. V.
Do Thuan
Lintz Paul R.
Marshall O'Toole Gerstein Murray & Borun
Westinghouse Process Control, Inc.
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