Controller for providing access to a video frame buffer in split

Details Controller for providing access to a video frame buffer in split Controller for providing access to a video frame buffer in split

1995-05-03

1998-11-17

Tung, Kee M.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395501, 395509, 395511, 395526, 395287, 395293, 345485, 345201, G06F 1516, G06F 1300

Patent

active

058389555

ABSTRACT:
A system includes a requesting agent coupled to a system bus. The system bus includes an address bus, control lines for indicating a requested transfer type, a data bus, address bus arbitration control lines and data bus arbitration control lines. The system further includes a system bus arbiter coupled to the system bus for resolving competing requests for access to the address bus and for separately resolving competing requests for access to the data bus. A graphics controller for enabling the requesting agent to access a frame buffer has a memory, which may be a FIFO, responsive to a first control signal, for storing data received from a frame buffer. The memory is further responsive to a second control signal for supplying the stored data to the data bus. The graphics controller also includes a controller coupled to the system bus and to the memory means. In response to a frame buffer read request from the requesting agent, the controller initiates a frame buffer read operation in accordance with parameters contained in the received frame buffer read request, and also initiates a request for access to the data bus. The first control signal is generated in response to data associated with the read request becoming available at an output of the frame buffer. The second control signal is generated in response to the requested access to the data bus being granted.

REFERENCES:
patent: 5257348 (1993-10-01), Roskowski et al.
patent: 5263138 (1993-11-01), Wasserman et al.
patent: 5274753 (1993-12-01), Roskowski et al.
patent: 5301272 (1994-04-01), Atkins
patent: 5388207 (1995-02-01), Chia et al.
patent: 5392407 (1995-02-01), Heil et al.
patent: 5469435 (1995-11-01), Krein et al.
patent: 5507026 (1996-04-01), Fukushima et al.
patent: 5511165 (1996-04-01), Brady et al.
patent: 5522061 (1996-05-01), Burgoon et al.
Patent Abstracts of Japan, vol. 12, No. 266 (P-735), 26 Jul. 1988 & JP, A, 63 052235 (Hitachi Limited), Mar. 5, 1988.
PowerPC 601 RISC Microprocessor User's Manual, pp. 2-42 through 2-70; 8-1 through 8-36; and 9-1 through 9-52, published by Motorola in 1993.
PCI Local Bus Specification, Review Draft Revision 2.1, published Oct. 21, 1994 by the PCI Special Interest Group, P.O. Box 14070, Portland, OR 97214.
PCI Multimedia Design Guide, Revision 1.0 (Mar. 29, 1994), which is distributed by the PCI Multimedia Working Group (part of the PCI Special Interest Group, P.O. Box 14070, Portland, OR 97214).

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