Controller for multiple instruction thread processors

Details Controller for multiple instruction thread processors Controller for multiple instruction thread processors

2005-08-16

2005-08-16

Donaghue, Larry D. (Department: 2154)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

C712S228000, C712S229000

Reexamination Certificate

active

06931641

ABSTRACT:
A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

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