Controller configurable for use with multiple memory...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

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Details

C711S005000, C711S154000, C365S051000, C365S230030, C365S230060

Reexamination Certificate

active

06298426

ABSTRACT:

BACKGROUND
The invention relates to a controller configurable for use with multiple memory organizations.
In a typical computer system, various types of memory components are used, such as main memory, video memory, cache memory, and buffers used in various cards in the computer system. The sizes of memory components in a computer system have increased rapidly.
The size selected for a memory subsystem is dependent at least in part upon the type of computer system. With higher-end computer systems, such as network servers or computers running graphics intensive applications, the size of each memory component may be large. In consumer desktop systems, laptop systems, and other lower-end systems, smaller memory components may be used.
Due to their relatively high access speeds and low cost, dynamic random access memories (DRAMs) or synchronous DRAMs (SDRAMs) are popular choices as storage devices. Sample chip sizes for DRAMs and SDRAMs include 16 megabits (Mb) and 64 Mb.
Various techniques are used to mount memory chips to a printed circuit board (e.g., the motherboard, video controller card, disk controller card, network controller card) in a computer system. One technique is to directly mount the memory chips to the board. To increase memory chip density, multiple memory chips are mounted onto memory modules having interconnecting pins for connection or coupling to sockets on the board. The memory modules may be configured as single in-line memory modules (SIMMs), double in-line memory modules (DIMMs), or other type modules (e.g., multichip modules). Multiple sockets may be provided on each board to receive multiple modules to increase memory capacity.
Because of the widely varying amounts of memory employed among different types of systems, the number of memory chips that may be used may also vary widely. A memory controller that is used to control a memory subsystem provides a number of control, address, and data signals. As the number of memory chips increases, the capacitive loads placed on the control, address, and data signals also increase. A large change in the load capacitance may cause a corresponding change in the switching characteristics of an output signal driven by the memory controller. Drivers in the memory controller typically have predefined current drive capabilities that may be used with a range of output load capacitances. However, because of the potential disparity in the number of chips used in higher-end systems and in lower-end systems, the load capacitances for driven signals may vary significantly. For improved performance, one type of memory controller (with a high current drive capability) may be used in the higher-end systems to control large memory subsystems, while a second type of memory controller (with a lower current drive capability) is used in lower-end computer systems.
SUMMARY
The invention in one embodiment is generally directed to a controller that is configurable to provide different output signal drive characteristics depending upon the memory organization used in a system.
In another embodiment, the invention features a memory controller for use with a memory subsystem of a selected configuration. A storage element stores a programmable value set according to the configuration selected for the memory subsystem. Output signal drivers are configurable by the programmable value in the storage element to provide an output characteristic.
In another embodiment, the invention features a method of controlling a memory subsystem having one of multiple organizations in a computer. The method includes determining the memory organization and configuring a memory controller coupled to the memory subsystem to have a predetermined output drive strength based on the determined memory organization.
Other features and advantages will become apparent from the following description and from the claims.


REFERENCES:
patent: 5873112 (1999-02-01), Norman
patent: 5895481 (1999-04-01), Yap
patent: 6060905 (2000-05-01), Bickford et al.
Intel Corp., “Peripheral Components,” pp. 1-1, 1-160 to 1-176, Nov. 1994.
Intel Corp., “Platform Components,” pp. 1-71, 80-93 (Jan. 1998).

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