Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-06
2004-01-20
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000, C438S197000
Reexamination Certificate
active
06680516
ABSTRACT:
BACKGROUND
Modern integrated circuits are constructed with up to several million active devices, such as transistors and capacitors, formed in and on a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polycrystalline silicon and metal, which are etched to form conductors for carrying signals. The conductive layers and interlayer dielectrics are deposited on the silicon substrate wafer in succession, with each layer being, for example, on the order of 1 micron in thickness.
A gate structure is an element of a transistor.
FIG. 1
illustrates an example of a gate stack
8
. A semiconductor substrate
10
supports a gate insulating layer
16
, which overlaps doped regions (source/drain regions) in the substrate (
12
and
14
), and the gate insulating layer supports a gate
18
, which is typically polycrystalline silicon. On the gate is a metallic layer
30
. The metallic layer may be separated from the gate by one or more other layers, such as nitrides, oxides, or silicides, illustrated collectively as barrier layer
20
. The metallic layer may in turn support one or more other layers (collectively
40
), such as nitrides, oxides, or silicides. Oxide
22
may be formed on the sides of the gate to protect the gate oxide at the foot of the gate stack; and insulating spacers
24
may be formed on either side of the gate stack. Furthermore, contacts to the source/drain regions in the substrate, and to the gate structure, may be formed.
Self-aligned contacts (SAC) allow the design of a semiconductor device to have a distance between the gate and the via contact to the substrate, to be at most one-half the minimum gate width; the contact may even be designed to overlay the gate. Typically, SAC uses a nitride layer on the gate stack, together with spacers that include nitride, to prevent a misaligned contact from electrically contacting the gate itself. If the nitride were not present, then the etch used to form the hole which will become the contact would pass through the dielectric layer all the way to the gate. When present, the nitride layer and spacers act as an etch stop, preventing misalignment from forming a hole all the way to the gate, and therefore allowing design of the device to have a much smaller average distance between the contact and the gate.
The nitride layer on the gate stack has at least a thickness of 800 angstroms when used for forming SAC. If used only for other purposes, such as an etch-stop layer or a hard mask, a thickness of less than 800 angstroms is used. Also, the thickness of at least 800 angstroms is the thickness after the dielectric layer has been formed; the nitride layer is usually thicker when originally formed, allowing for a loss of about 500 angstroms during the gate etch (i.e. thickness for the hard mask function), and a loss of about 200 angstroms during nitride spacer formation.
There is an ongoing need to reduce the size of the elements within integrated circuits and semiconductor structures. As the size of an element is reduced, it does not necessarily follow that the thickness of specific layers that form that element can be equally reduced: for example, the thickness of a nitride layer necessary for forming SAC may still need to be at least 800 angstroms. This could lead to designs for devices that require large aspect ratios for contact vias; such vias may not be properly filled.
BRIEF SUMMARY
In a first aspect, the present invention is a semiconductor structure, comprising a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.
In a second aspect the present invention is a semiconductor structure, comprising a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, an etch-stop layer on the metallic layer, an insulating layer on the etch-stop layer and on the substrate, and a via through the insulating layer on the substrate. An area of contact between the via and the substrate has a via width, and the via width is at most 0.12 micron. In addition, a distance between the substrate and a top of the etch-stop layer has a gate stack height, and the gate stack height is at most 2700 angstroms.
In a third aspect, the present invention is a method of making a semiconductor structure, comprising forming a gate layer on a semiconductor substrate, forming a metallic layer on the gate layer, and forming an etch-stop layer having a thickness of at least 1500 angstroms on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms.
The term “distance” means the length between the closest edges of the two objects.
REFERENCES:
patent: 6541830 (2003-04-01), Iyer
patent: 6552401 (2003-04-01), Dennison
Encyclopedia of Chemical Technology, Kirk-Othmer, vol. 14, pp. 677-709 (1995).
Diaz, C.H., H. Tao, Y. Ku, A. Yen, and K. Young, 2001. “An Experimentally Validated Analytical Model For Gate Line-Edge Roughness (LER) Effects on Technology Scaling”, IEEE Electron Device Letters, 22(6)287-289.
Blosse Alain
Ramkumar Krishnaswamy
Cypress Semiconductor Corp.
Prenty Mark V.
Sonnenschein Nath & Rosenthal LLP
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