Controlled slew rate output buffer

Details Controlled slew rate output buffer Controlled slew rate output buffer

1994-09-14

1996-05-21

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 87, 326 85, H03K 1902, H03K 1716

Patent

active

055193382

ABSTRACT:
An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices coupled between the common output node and the base of the pull-down bipolar transistor. A second set of parallel MOS devices are coupled between the base of the pull-up output stage bipolar transistor and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

REFERENCES:
patent: 4902914 (1990-02-01), Masuoka
patent: 5059821 (1991-10-01), Murabayashi et al.
patent: 5216293 (1993-06-01), Sei et al.
patent: 5218239 (1993-06-01), Boomer
patent: 5243237 (1993-09-01), Khieu

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