Controlled selective disconnect system for wafer scale integrate

Details Controlled selective disconnect system for wafer scale integrate Controlled selective disconnect system for wafer scale integrate

1980-06-09

1982-05-11

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

365 96, H04Q 900, G11C 1700

Patent

active

043296858

ABSTRACT:
This disclosure relates to a controlled selective power disconnect means for employment with the various circuits implemented on a crystalline wafer so that a particular circuit can be selectively disconnected when it has developed a defect or short or is unwanted in the system for other reasons. The disconnect means employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be melted or blown by a power disconnect signal thereby opening the gate. An amorphous switch can also be used such that networks can expand or contract around defective chips as required by the particular task or tasks involved.

REFERENCES:
patent: 3691538 (1972-09-01), Haney et al.
patent: 3909805 (1975-09-01), Touron et al.
patent: 3940740 (1976-02-01), Coontz
patent: 4056807 (1977-11-01), Thornber
patent: 4151611 (1979-04-01), Sugawara et al.

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