Controlled prefetching of data requested by a peripheral

Details Controlled prefetching of data requested by a peripheral Controlled prefetching of data requested by a peripheral

1997-06-05

1998-07-28

Shin, Christopher B.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711159, 359853, G06F 700

Patent

active

057874751

ABSTRACT:
A method and apparatus for determining when an Input/Output (I/O) module should prefetch cache lines of data from main memory. Following a request for data from a peripheral, connected to an I/O bus which supports a flexible protocol allowing peripherals with various capabilities to operate, the I/O module will request a cache line of data from main memory containing a beginning portion of the requested data. The I/O module may then prefetch consecutive cache lines containing requested data according to the operating parameters of the peripheral requesting the data and the requested data. The I/O module may prefetch in such way that neither system bus bandwidth nor I/O bus bandwidth is wasted.

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