Controlled PMOS load on a CMOS PLA

Details Controlled PMOS load on a CMOS PLA Controlled PMOS load on a CMOS PLA

1996-12-26

2001-04-24

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S045000, C326S041000

Reexamination Certificate

active

06222383

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to programmable logic array (PLA) circuits and, in particular, to the use of a controlled load in either the AND plane or the OR plane, or both, of a CMOS PLA for logical functionality, speed, power and area purposes.
2. Discussion of the Related Art
FIG. 1
shows a generic CMOS programmable logic array (PLA)
10
that consists of a set of input latches
12
, output latches
14
, an AND plane
16
and an OR plane
18
. As shown in the accompanying timing diagrams, at the beginning of each cycle, inputs are clocked into the input latches
12
. From the input latches
12
, the signals are fed into the AND plane
16
where minterms are generated. These minterms are then fed into the OR plane
18
where the various minterms are “OR-ed” together to form the sum of products. The sum of the products are then latched into the output latches
14
to be used by the rest of the system.
CMOS PLA circuits can be implemented easily using pseudo NMOS NOR gates. As shown in
FIG. 2
, a pseudo NMOS NOR gate
20
includes parallel-connected NMOS transistors
22
with a single PMOS transistor
24
to form the load. The gates of NMOS transistors
22
form the inputs to the NOR gate
20
and the gate of the PMOS transistor
24
is tied to ground GND. The common drain nodes of the PMOS transistor
24
and the NMOS transistors
22
form the gate output node.
To implement a pseudo NMOS NOR PLA, DeMorgan's rule is used to form the AND and OR planes. By inverting the inputs to a set of pseudo NMOS NOR gates, the AND plane is constructed; by inverting the outputs of a set of pseudo NMOS NOR gates, the OR plane is constructed. An example of this type of PLA is shown in FIG.
3
.
The advantage of the
FIG. 3
implementation is that the design is straightforward. No other timing signals are needed in this design other than the clocks to the input and output latches. The disadvantages of this implementation are the size and power considerations common to all pseudo NMOS NOR gates. If one of the inputs to the pseudo NMOS NOR gates is high, static power is consumed since both NMOS and PMOS transistors are on. Also, the NMOS transistors must be larger than the PMOS transistor by several factors (e.g., 3× in the
FIG. 2
gate) to obtain a good VOL or low output voltage. If all inputs happen to switch low, then the PMOS load transistor must be large enough to drive all the NMOS drains and the wiring capacitance to a high at the output node. In a PLA, these disadvantages are exacerbated. In the AND and OR planes, the number of inputs and the wiring length at the output node are non-trivial. This results in an implementation that is relatively large, limited in speed and consumes static power.
CMOS PLA's can also be implemented using dynamic OR gates for both the AND and OR planes. The dynamic OR gate is similar to a generic dynamic OR gate except that the ground switch transistor may be removed to keep the gate size to a minimum. Simple dynamic OR gates with and without the switch transistor are shown in FIG.
4
A and
FIG. 4B
, respectively.
Referring to FIG.
5
and its associated timing diagrams, similar to the pseudo NMOS PLA, the dynamic PLA uses DeMorgan's rule for the AND plane. Although a dynamic AND gate can be used to implement the AND plane, a dynamic OR gate is used to avoid an excessive NMOS stack. The inverted output signals from the input registers are fed into a set of dynamic OR gates to form a NAND plane. The outputs of the dynamic NAND plane are inverted to finally complete the logical equivalent of an AND plane. Since this implementation results in the outputs of the AND plane being high during the precharge phase, the design must accommodate this condition. If switch transistors are used in the design, then timing margin must be added between the end of the evaluation period of the AND plane and the beginning of the evaluation period of the OR plane. If a switch transistor is not used, then, as in the
FIG. 5
circuit, a resetting latch must be added at the AND/OR plane interface to ensure that all inputs to the OR plane are low during its precharge phase. To construct the OR plane, a set of dynamic OR gates is arrayed to fit against the AND plane.
There are several advantages of speed and power to the dynamic PLA implementation. Unlike the pseudo NMOS NOR implementation, there is no static power dissipation. Since the NMOS transistors in the dynamic OR gates are only used to pull down charge during the evaluation period, the size of these transistors and, therefore, the size of the whole array can be kept to a minimum. The disadvantage of the dynamic PLA is that the timing and, therefore, the circuit design, is considerably complex. Although dynamic circuits are relatively fast, timing margin must be added to guarantee functionality over all possible environmental and manufacturing conditions. The addition of timing margin increases the propagation delay (clock to outputs) of the PLA. For both the precharge and evaluation intervals, timing margin must be added to ensure that the outputs of the dynamic gates reach full high and low output levels. This addition of timing margin is necessary for both switch and non-switch transistor dynamic PLA designs. As previously mentioned, the switch-transistor PLA design must accommodate larger AND and OR planes due to the switch transistors; the non-switch transistor PLA design must accommodate a resetting latch between the AND and OR planes. These factors add to the overall propagation delay and the complexity of the dynamic PLA designs.
SUMMARY OF THE INVENTION
The present invention reduces the size and power of PLA's in comparison with pseudo-NMOS NOR PLAs. In comparison to dynamic PLAs, the invention reduces overall propagation delay and complexity in the design.
Referring to
FIG. 6
, the invention provides a pullup circuit function
100
by means of a PMOS transistor
102
. The pullup circuit function
100
is similar to a static pseudo NMOS NOR gate utilizing the single PMOS transistor
102
and several NMOS transistors
104
. However, in accordance with the invention, the source of the PMOS transistor
102
is connected to VDD and the gate of the PMOS transistor
102
, unlike the pseudo static NMOS NOR gate, is connected to a timing chain. The drain of the PMOS transistor
102
is connected to the drains of NMOS transistors
104
which form the output of the NOR gate. The inputs are the gates of the NMOS transistors
104
. All of the sources of the NMOS transistors
104
are connected to ground. The resulting invention is a controlled PMOS pullup circuit that implements a logical NOR function.
To generate the AND function with the circuit
100
, DeMorgan's rule is used. Since this invention performs a logical NOR function, inverting the inputs to this circuit results in the AND function. To generate the OR function, a normal CMOS inverter is added to the output of the circuit
100
.
In one particular embodiment of the invention, shown in
FIG. 7
, a set of input registers
106
, a set of output latches
108
and a dynamic AND plane
110
are used with an OR plane
112
containing the invention. At the beginning of any clock cycle, input values are clocked into the input registers
106
. Using the outputs from the input registers
106
, the AND plane
110
generates minterms. As the minterms are generated at the output of the AND plane
110
, the set of self-timed circuits
114
asserts a signal to turn on the PMOS load transistor. As the signals propagate through the OR plane
112
, the sum of the products outputs of the OR plane
112
are latched and the PMOS pullup transistors
102
in the OR plane are turned off.
It is important to note that, like the dynamic case, although a self-timed circuit
114
is used to control the PMOS load transistor
102
, this transistor is sized similarly to the PMOS transistor in the pseudo NMOS NOR gate. This means that, unlike the dynamic gate, the timing of the self-timed signal is no longer crit

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