Controlled output impedance buffer using CMOS technology

Details Controlled output impedance buffer using CMOS technology Controlled output impedance buffer using CMOS technology

1998-06-22

2000-07-11

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326 86, 326 87, H03K 190175

Patent

active

060878533

ABSTRACT:
CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.

REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5334885 (1994-08-01), Morris
patent: 5382847 (1995-01-01), Yasuda
patent: 5457407 (1995-10-01), Shu et al.
patent: 5559447 (1996-09-01), Rees
patent: 5563539 (1996-10-01), Takase
U.S. Ser. application No. 09/083,172 filed May 22, 1998 Gabara et al.

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