Controlled load limited switch dynamic logic circuitry

Details Controlled load limited switch dynamic logic circuitry Controlled load limited switch dynamic logic circuitry

2006-10-31

2006-10-31

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S096000

Reexamination Certificate

active

07129754

ABSTRACT:
An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.

REFERENCES:
patent: 5757205 (1998-05-01), Ciraula et al.
patent: 6459316 (2002-10-01), Vangal et al.
patent: 6567337 (2003-05-01), Sprague et al.
patent: 6873188 (2005-03-01), Belluomini et al.

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