Controlled delay digital clock signal generator

Details Controlled delay digital clock signal generator Controlled delay digital clock signal generator

1993-12-16

1995-08-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Slope control of leading or trailing edge of rectangular or...

327172, 327131, 327134, 327269, H03K 512

Patent

active

054382912

ABSTRACT:
Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.

REFERENCES:
patent: 4117757 (1978-10-01), Akamatu
patent: 4124821 (1978-11-01), Petr
patent: 4277753 (1981-07-01), Faulkner
patent: 4839788 (1989-06-01), Tullsen
patent: 5045800 (1991-09-01), Kung
patent: 5140591 (1992-08-01), Palara et al.

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