Controllably switched phase locked loop circuits, systems, and m

Details Controllably switched phase locked loop circuits, systems, and m Controllably switched phase locked loop circuits, systems, and m

1996-11-26

1998-04-14

Heckler, Thomas M.

Computer graphics processing and selective visual display system

Computer graphics display memory system

First in first out

331 25, 331 1A, 375376, H03L 706

Patent

active

057404119

ABSTRACT:
Circuits, systems, and methods, relating to a controllably switched phase locked loop. The system indudes a phase locked loop circuit (16) having a clock signal input (16c), a clock signal lock input (16a), and a clock adjustment signal input (16b). The system further includes circuitry (12c) for coupling a clock signal to the clock signal input, circuitry (28) for coupling a first clock adjustment signal to the clock adjustment signal input, and circuitry (24) for comparing the first clock adjustment signal to a second clock adjustment signal. Lastly, the system includes circuitry responsive to the comparing circuitry. This responsive circuitry includes firstly, circuitry (26) for coupling a signal to the clock signal lock input such that the phase locked loop circuit indicates an unlocked state, and secondly circuitry (22, 28) for coupling the second clock adjustment signal to the clock adjustment signal input after the phase locked loop circuit indicates an unlocked state.

REFERENCES:
patent: 4602225 (1986-07-01), Miller et al.
patent: 4829258 (1989-05-01), Volk et al.
patent: 4972442 (1990-11-01), Steierman
patent: 5126690 (1992-06-01), Bui et al.
patent: 5128632 (1992-07-01), Erhart et al.
patent: 5506531 (1996-04-01), Jang et al.

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