Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2005-01-04
2005-01-04
Myers, Paul R. (Department: 2111)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S039000, C710S112000, C710S113000, C710S119000
Reexamination Certificate
active
06839784
ABSTRACT:
A virtual channel buffer of a transaction scheduler in a computer system I/O node. A control unit includes a plurality of scheduler units. Each scheduler unit may include a first and a second buffer circuit. The first buffer circuit may include a first plurality of buffers and the second buffer circuit may include a second plurality of buffers, each of which are coupled to receive control commands from a first and second source, respectively. Each buffer of the first and the second plurality of buffers corresponds to a respective virtual channel of a plurality of virtual channels and may be configured for storing selected control commands that belong to said respective virtual channels. Each scheduler unit may also include an arbitration unit for arbitrating between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit.
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U.S. Appl. No. 09/399,281, filed Sep. 17, 1999.
Berndt Paul W.
Ennis Stephen C.
Advanced Micro Devices , Inc.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Myers Paul R.
Phan Raymond N
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