Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-09-07
2004-07-13
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
15, 15
Reexamination Certificate
active
06763437
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to access to a memory device by at least two controllers, and more particularly to a bus control protocol for providing memory access to the controllers.
BACKGROUND OF THE INVENTION
Storage devices such as disk drives are used in various systems such as computer systems and audio/visual systems (e.g., Digital VCR (DVCR)) for data storage. A typical disk drive comprises a head structure including one or more read/write heads moved by a support arm of an actuator assembly via a voice coil motor across tracks of one or more disks for data storage and data retrieval. The disk drive further includes drive electronics comprising a preamplifier/write driver circuit connected to the actuator assembly so that electrical signals may reach the heads. The signals leaving and entering the drive electronics are utilized by a drive microcontroller and other electronics including a motors control Application Specific Integrated Circuit (ASIC) which supplies driving signals to operate a spindle motor and the actuator, a Partial Response Maximum Likelihood (PRML) read/write channel ASIC which receives and decodes coded data from the disk and which encodes and delivers coded data to the write driver portion of the channel.
The disk drive further includes a disk drive controller ASIC implementing a SERbES/ENDEC function, an Error Correction Code (ECC) function, a data sequencer, a memory controller, a bus level interface, and a microprocessor interface for interfacing a microprocessor with other circuits including a Dynamic Random-Access Memory (DRAM) buffer which contains microprocessor program instructions as well as data blocks being transferred between a host and the data storage disk. An internal data,.address, control bus structure interconnects the microprocessor, motors control ASIC, PRML read/write channel ASIC, the disk drive controller ASIC and the DRAM buffer chip. A connection from the disk drive controller ASIC to host computing equipment is provided by a drive interface bus.
However, a disadvantage of such a disk drive is that the disk drive controller ASIC handles all DRAM buffer access protocol, such that all data transfer between the DRAM buffer and the disks, and data transfer between the DRAM buffer and the host is handled by the disk drive controller ASIC. Therefore, all features required for supporting host data transfer for different hosts (e.g., DRAM buffer access requirements for data transfer between the host and the DRAM buffer) must be included in the disk drive controller ASIC. For example, the disk drive controller ASIC must support differing host transfer features for both Audio/Video (A/V) products and for computer systems. As such, the disk drive cannot be used in conjunction with a new host system unless the disk drive controller ASIC is modified to include host data transfer features required for the host system. A new disk drive controller ASIC is required everytime the disk drive is used in a new host system with new features not included in the disk drive controller ASIC. This increases the disk drive controller ASIC redesign cycles, increasing costs.
There is, therefore, a need for a control system and access protocol for controlling access to a shared memory that alleviates the above problems. There is also a need for such a control system for a disk drive such that data transfer between the disks and a shared buffer memory in the disk drive is decoupled from the host system data transfer between the host system and the disk drive memory buffer. There is also a need for a buffer access protocol for providing buffer memory access for data transfer between the disks and the buffer memory and for data transfer between the host system and the buffer memory. There is also a need for such a disk drive to be usable with different host systems having different data transfer requirements.
BRIEF SUMMARY OF THE INVENTION
The present invention satisfies these needs. In one embodiment, the present invention provides a method and control system of providing access to a memory interconnected to a first controller and a second controller via a bus, the bus for transferring data between the first controller and the memory, and between the second controller and the memory, the bus having control signals associated therewith for data transfer control and communication between the first and the second controllers. The second controller transmits an access request to the first controller for bus control to access the memory; and in response, the first controller selectively grants the access request and transmits an acknowledge to the second controller. Upon receiving the acknowledge, the second controller accesses the memory for data transfer.
In one version, the first controller can have a higher priority for accessing the memory and the second controller, such that upon an access request the first controller selectively grants bus control to the second controller for, memory access, otherwise the first controller maintains bus control for memory access. However, upon access request from the first controller, the second controller relinquishes bus control unconditionally. In one embodiment, each of the controllers relinquishes control of the bus by placing the bus in “tristate”, wherein the relinquishing controller stops driving the bus.
Such a memory access control method and system according to the present invention can be utilized in any application where controlling access to a shared memory by two or more controllers is required. For example, according to one aspect of the present invention, data transfer between the disks and a shared buffer memory in the disk drive is decoupled from a host system data transfer between the host system and the memory buffer. As such, a bus is connected to the memory, wherein a storage controller (first controller) connected to the bus handles data transfer between the disks and a shared buffer memory via the bus, and a host interface (second controller) connected to the bus handles data transfer between the host system and the memory buffer via the bus. The storage controller and the host interface communicate therebetween for handshaking to access the memory via the bus without contention.
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Brooks John W.
Gill Parminder K.
Nguyen Hang
Nguyen Trung
Gossage Glenn
Maxtor Corporation
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