Control system of FIFO memories

Details Control system of FIFO memories Control system of FIFO memories

1997-11-03

2000-06-20

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

710 20, 710 21, 710131, 711148, G06F 1300, G06F 300

Patent

active

060789727

ABSTRACT:
To reduce access frequency to a CPU for recording/reproducing digital audio data, a control system of FIFO memories of the invention applied to an sound codec apparatus comprises means (2, 4, 7, 9 and 10) for controlling a first and a second FIFO memory (3 and 8) to store recording data sequentially and to output stored recording data sequentially when the apparatus is used exclusively for recording; and controlling the first and the second FIFO memory to store the reproducing data sequentially and to output the stored reproducing data sequentially when the apparatus is used exclusively for reproducing.

REFERENCES:
patent: 5535356 (1996-07-01), Kim et al.
patent: 5550566 (1996-08-01), Hodgson et al.
patent: 5680151 (1997-10-01), Grimm et al.
patent: 5748984 (1998-05-01), Sugita
patent: 5835787 (1998-11-01), Raffman et al.
patent: 5900830 (1999-05-01), Scheffler
Traffic Management Specification Version 4.0, The ATM Forum, Mar. 1996.

Affiliated with

Also associated with

Rating

Control system of FIFO memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Control system of FIFO memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control system of FIFO memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1863722