Data processing: generic control systems or specific application – Specific application – apparatus or process – Article handling
Reexamination Certificate
2000-03-02
2001-04-24
Ellis, Christopher P. (Department: 3651)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Article handling
C700S109000, C700S115000, C700S012000, C209S571000, C209S573000, C702S081000, C702S082000, C702S083000, C702S084000
Reexamination Certificate
active
06223098
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing of integrated circuit devices. More particularly, the present invention is directed to a control system and a control method for controlling test procedures by processing test data generated from the test procedures and analyzing the test data.
2. Background of the Related Art
In general, semiconductor IC devices are fabricated via hundreds of processing steps, and must be subjected to a variety of test processes to verify their electrical function, performance, and reliability prior to shipment. The test processes include, among others, a final test and a quality assurance (QA) test. In the final test, all of the IC devices that have passed through the wafer fabrication steps and assembly processing steps are tested and sorted into good or failed devices. The final test may be performed on a number of identical IC devices manufactured under the same processing environment, for example, up to two thousand devices at once.
According to the results of the final test, the IC devices are classified in certain bin categories. For example, IC devices classified as BIN
1
(i.e., bin category
1
), have experienced no failures and are thus regarded as good or passed devices, while IC devices classified as BIN
7
(i.e., bin category
7
) are regarded as defective devices with the main cause of failure being excessive leakage current. Of course, any number of bin categories and bin numbering systems may be employed depending on the semiconductor manufacturer and the nature of the IC devices to be tested. For example, other bin categories could accommodate failures due to voltage or current being outside an acceptable range, open/short failures, or differing memory access times.
The QA test is used to confirm the results of the final test and to assure the quality of the devices requested by specific customers by testing predetermined numbers of devices sampled from the good devices (e.g., BIN
1
devices) that have passed the final test. After passing the QA test, the good devices are delivered to the customers.
Present day semiconductor markets call for multiple species of small quantity, high technology and short life cycle devices. Due to the short life cycle and specialized nature of the devices, manufacturers who develop and sell new IC devices require the ability to quickly set-up the production lines, as well as have fast, accurate analysis of the causes of failures so as quickly correct defects in the production line. Furthermore, the time required for testing should also be reduced as much as possible without sacrificing quality or reliability. To do so, the manufacturers need to control the overall test procedures and to integrally manipulate test data. In order to stabilize the product lines and produce high quality devices, failure analysis and test data should be made readily available to the designers and production personnel so that changes may be reflected in circuit design, wafer fabrication, and assembly steps.
SUMMARY OF THE INVENTION
The present invention provides a control system and control method which: improves the efficiency of the test process; reduces test time; accurately analyzes test data and stabilizes the production lines; bypasses the QA sampling test by using test data of the final test; and efficiently controls the final test procedure by analyzing test results in real time during the final test.
To achieve these and other advantages, the present invention provides a control system for controlling the test processes of IC devices. The control system includes testers for testing plural electrical characteristics of the IC devices, a host computer for processing data transmitted from testers and for creating a number of databases structures in the host computer memory, and distributed computers for monitoring the test progress and analyzing the test results using the database structures stored in the host computer.
The database structures stored in the host computer include a lot decision database for determining the subsequent flow path of a tested lot after a final test, a test progress monitoring database and a test data analysis database. The lot decision database includes a test program name, a lot number, and the number of IC devices sorted into each of the bin categories based on the test sequences performed by the testers. The test progress monitoring database includes a tester name, a test mode, a lot size, total count, total failed devices, good devices, open/short failures, and the other failures. The test data analysis database includes a device name, a test program name, a test board identification, a test start time, a lot size, total count, total failed, and the number of IC devices sorted into each of the bin categories.
A control method of the present invention comprises the steps of: setting up IC devices to be tested and loading test programs; performing a final test by lot; monitoring the progress of the final test while storing test data during the final test; determining if the final test is completed; performing a lot decision after the final test is completed based on the bin category limits established by a bin category limit determining sequence; displaying the lot decision result and storing the test data; requesting an incoming inspection according to the lot decision result; and performing Q/A monitoring.
In the lot decision sequence of the present invention, it is determined if any bin category exceeding their bin category limit is greater than a certain predetermined value even though the lot meets the yield requirement. All test data generated during the final test are stored into a central host computer according to the bin category so that the test data can be readily compared with their bin category limits.
For setting the bin category limits, various criteria are applied depending on whether the bin categories are related to the yield requirement of the devices (e.g., BIN
1
), to the electrical characteristics (e.g., open/short failures or leakage current), or to other characteristics of the IC devices. The bin category limits should be defined on the basis of the number of good or passed devices in a lot having a yield ranging from 95% to 100%, and the bin category limits should be set only after a sufficient number of lots have been tested and a certain amount of test results have been stored. Further, the bin category limits are applied differently depending on the ratios of failed devices to their corresponding bin category.
Cheong Kwang Yung
Kim Jae Young
Lee Ann Seong
Dillon, Jr. Joe
Ellis Christopher P.
Jones Volentine, L.L.C.
Samsung Electronics Co,. Ltd.
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