Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1999-07-28
2001-08-07
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S029000, C710S030000, C710S031000, C710S060000, C710S062000
Reexamination Certificate
active
06272569
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to analog and digital signal processing, and more particularly, to a combined analog front end and digital signal processing integrated circuit.
2. Description of Related Art
Digital signal processors provide pipeline processing of digital information. The digital information typically is provided by analog to digital converters that convert an analog signal, such as voice, into digital signals. Digital signal processors and analog to digital converters typically are designed separately and serially process data without regard to optimizing the data processing.
It is desired to have a combined analog front end and digital signal processing circuit that is designed to work with host processors such as a RISC processor.
SUMMARY OF THE INVENTION
The present invention provides a modem interface circuit that includes a memory, an analog interface and a digital signal processor. The memory is configured to be accessed by an external host processor. The analog interface communicates data with an external modem and converts analog data received from the external modem to digital data, and converts digital data to analog data for communication with the external modem. The digital signal processor processes the digital data and stores the processed data in the memory. The digital signal processor provides an interrupt to the external host processor to request that the host processor communicate data between memory and the host processor.
The memory may include a register for storing an interrupt clear signal indicative of the host processor completing the servicing of the interrupt. The analog interface and the digital signal processor may communicate data by storing the data in the memory. In response to an interrupt from the analog interface, the digital signal processor retrieves data stored in the memory by the analog interface.
The present invention provides a computer that includes a host processor, an analog interface, and a digital signal processor. The host processor is configured to execute signal processing at a first processing rate code for processing symbols including digital data indicative of a received analog signal. The analog interface communicates data with an external communication unit, such as a modem, and converts analog data received from external communication unit to digital data and converts digital data to analog data for communication with the external communication unit. Such conversion is performed at a sampling rate of the analog interface according to the present invention. The digital signal processor processes the digital data representative of the analog signal at a second data rate, such as the sampling rate of the analog interface. The host processor processes data at a symbol rate of the data according to the present invention. Such partition of the processing between the host processor and the digital signal processor allows the digital signal processor to process data at rates comparable to the sampling rate of the analog interface and in turn at the rate of received data. The host processor executes signal processing at slower rates, typically at the symbol rate of data that is to be communicated with the external communication unit.
The present invention further provides an interface circuit having a sleep mode for reduced power consumption. The interface circuit particularly includes a digital signal processor and an analog interface. The digital signal processor has a sleep mode in which the digital signal processor draws a sleep current and has an operational mode in which the digital signal processor draws an operational current that is greater than the sleep current. The digital signal processor enters the operational mode in response to a wake-up signal, and enters the sleep mode after a predetermined event while in the operational mode. The predetermined event may be, for example, a time interval during which no external signal is received. The analog interface receives a ring detect signal from a modem, for example, and provides a wake-up signal to the digital signal processor in response to the ring detect signal. The digital signal processor may then provide an interrupt to an external host processor to indicate that the digital signal processor is in an operational mode.
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Technical Manual for 3 Com 3C905B-TX PCI Ethernet Card, 3 Com Confs, 1998.
Cirrus Logic Inc.
Lin Steven
Shin Christopher B.
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