Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-07-19
1998-04-21
Coleman, Eric
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, G06F 1580
Patent
active
057428433
ABSTRACT:
When the processor writes a command data string into an address of the command entry area, a corresponding command is created by a bus interface. If an address output by the processor corresponds to a distributed shared memory area, the bus interface creates a remote access command. The send controller constructs a message based on the command created by the bus interface. This message is sent either to an interconnection network, or to a receive controller. The receive controller receives the message and interprets it. An address output by the processor is detected by a cache area access unit, and the cache area in the memory is accessed. When the processor receives an interrupt request while waiting for a response message to a remote read request, an deadlock control unit detects an abnormal end of the remote read request that the remote read has ended in an error, and, controls the processor to process the interrupt request with priority.
REFERENCES:
patent: 5165023 (1992-11-01), Gifford
patent: 5347639 (1994-09-01), Rechtschaffen
patent: 5537569 (1996-07-01), Masubuchi
patent: 5613136 (1997-03-01), Casavant
Horie Takeshi
Ishihata Hiroaki
Koyanagi Yoichi
Shimizu Toshiyuki
Shiraki Osamu
Coleman Eric
Fujitsu Limited
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