Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-04-22
1998-06-09
Robertson, David C.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
395842, G06F 1300
Patent
active
057651876
ABSTRACT:
A receiving buffer control system comprises a memory having a buffer area serving as a receiving buffer, data being applied to the memory via a bus, a write pointer indicating a write address of the buffer area, and a read pointer indicating a read address of the buffer area. An overrun/underrun detection circuit detects a situation in which an overrun or an underrun will occur in the buffer area in response to the write address indicated by the write pointer and the read address indicated by the read pointer. A control part disables the data from being written into and read out from the buffer area when the overrun/underrun detection circuit detects the situation.
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Horie Takeshi
Ishihata Hiroaki
Shimizu Toshiyuki
Fujitsu Limited
Robertson David C.
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