Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-12-28
2004-11-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C438S011000, C438S015000, C438S025000, C438S106000, C257S048000, C257S678000, C716S030000
Reexamination Certificate
active
06815230
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit package and, more particularly, to a control signal transmitting method and the related structure of an integrated circuit package.
2. Description of the Related Art
In fabricating a semiconductor integrated circuit such as a random access memory, one or more additional I/O pad is typically used for providing testing, diagnostic or other control functions. For instance, the additional pad can be used as a pad to communicate test signals such as for a wafer burn-in test, where temperature and voltage stress are applied to a plurality of memory cells selected at the wafer level to screen initial failures. Other tests may include a merged-DQ test to simultaneously test a plurality of inputs/outputs, and parallel BIT test to simultaneously test a plurality of memory cells. Testing performed at the early stage of semiconductor manufacture increases reliability and thus the yield efficiency of the semiconductor device.
In the case where tests are performed with the additional or option pad at the wafer level where integrated circuit chips are included on the wafer, there have been limitations of the tests because the option pad cannot be accessed at the package level. As the specification sizes and pin outs of packages are standardized, an extra pin or an option pin cannot be easily provided. In other words, it is very difficult to randomly provide an option pin to be connected with the option pad while the structure of package pins is particularly specified. Thus, various tests are not effectively performed at the package level, thereby lowering productivity yield.
To provide more thorough understanding of the above problems, a description will be made with reference to the accompanying drawings.
Referring to
FIG. 1
, a general integrated circuit package is constructed in an integrated circuit chip
10
with a receiving unit
12
as an internal circuit, a wafer pad unit
13
, and a package pin unit
21
as an integrated circuit package by mounting and packaging the integrated circuit chip
10
at a lead frame. The receiving unit
12
includes a control receiver
1
, an option receiver
2
and a power (VSS/VDD) line
3
. The wafer pad unit
13
includes a control pad and electrostatic discharge (ESD) circuit
4
, an option pad
5
, and a plurality of power pads
6
and
7
. The package pin unit
21
includes a control pin
22
and power pins
23
and
24
connected to the corresponding plurality of power pads
6
and
7
.
In the structure shown in the
FIG. 1
, the option pad
5
is exposed outside at the wafer level, so that a predetermined control signal can be provided through the option pad
5
to the option receiver
2
to perform desired tests. However, it is impossible to perform desired tests after completion of all packaging because a package pin is not available for connection with the option pad
5
. Thus, to perform a test with the option pad, it is necessary to provide an additional package pin on the package. However, it is very difficult to additionally provide an option pin to be connected with the option pad because a specification of package assembly type is standardized.
SUMMARY OF THE INVENTION
A method for transmitting a control signal to an option pad of an integrated circuit chip at its package level is provided, which includes the steps of: electrically isolating one of a plurality of commonly connected power transmitting pins of the integrated circuit package; connecting the electrically isolated power transmitting pin to the option pad to thereby transmit a control signal from outside through the electrically isolated power transmitting pin to the option pad.
According to an embodiment of the present invention, the commonly connected power transmitting pins is connected to ground or a power supply. The option pad is a pad for performing a burn-in test at the package level. The control signal is an external signal to perform one of burn-in test, input/output test, and parallel bit test.
According to an embodiment of the present invention, the integrated circuit package includes a ball grid array pin arrangement, and includes a static random access memory device.
An integrated circuit package having an integrated circuit chip for transmitting a test control signal from outside is also provided, which includes: the integrated circuit chip being mounted in the integrated circuit package with power pads connected with an option pad and power lines connected to an internal circuit; power transmitting group pins connected to the power pads of a plurality of power transmitting pins assigned and formed at the integrated circuit package; and at least one signal transmitting pin connected to the option pad but electrically isolated from the power transmitting group pins.
According to an embodiment of the present invention, the power pads are ground voltage pads when the power transmitting pins are ground voltage pins, and the power pads are power supply voltage pads when the power transmitting group pins are supply power voltage pins. The option pad is a pad for performing a burn-in test at the package level. The control signal is an external signal to perform one of burn-in test, input/output test, and parallel bit test.
According to an embodiment of the present invention, the integrated circuit package includes a ball grid array pin arrangement and a static random access memory device. The option pad includes an electric static discharge circuit, and includes a keeper circuit to prevent a false operation of a device when the signal transmitting pin is open. The internal circuit is constructed with an option receiver having an inverter structure.
A method for performing a test by controlling an internal circuit of a package chip at the package level is also provides, which includes the steps of: connecting a power transmitting pin to an option pad, the option pad being accessible only at the wafer level; isolating the power transmitting pin from a plurality of power transmitting pins commonly connected to one of power and ground; and transmitting a test control signal to the option pad through the power transmitting pin.
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Cho Uk-Rae
Park Yong-Dae
F. Chau & Associates LLC
Lee, Jr. Granvill D.
Samsung Electronics Co,. Ltd.
Smith Matthew
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