Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-09-14
2004-05-11
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S714000, C438S719000
Reexamination Certificate
active
06734088
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor processing, and, more particularly, to the field of forming gate electrodes on a semiconductor device, e.g., a transistor.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
As device dimensions have continued to decrease, the process of forming the gate electrode of a transistor have become more critical. By way of background,
FIG. 1
depicts a partially formed transistor
10
comprised of a gate electrode
16
and a gate insulation layer
14
. The gate electrode
16
has a top surface
15
. In general, the structure depicted in
FIG. 1
may be formed by forming the appropriate process layers above a semiconducting substrate
12
and, thereafter, performing one or more etching operations to define the gate electrode
16
and the gate insulation layer
14
. The gate insulation layer
14
may be comprised of a variety of insulating materials, such as silicon dioxide, and the gate electrode
16
may be comprised of a variety of materials, although it is normally comprised of polysilicon in modern devices.
Typically, in modern device fabrication, a two-step etch process is used to pattern the gate electrode
16
. Initially, a timed etch process, sometimes referred to as a main etch, is performed to etch through the bulk of the thickness of the layer of material, e.g., polysilicon, from which the gate electrode
16
will be formed. With reference to
FIG. 2
, which is an enlarged and exaggerated view of a portion of the device shown in
FIG. 1
, this timed etch process may be performed in the region indicated by line
23
. This timed etch process is normally performed using an etching recipe that does not have a high degree of selectivity with respect to silicon dioxide, a common material used for the gate insulation layer
14
. However, the timed etch process typically does produce a relatively straight sidewall
18
of the gate electrode
16
in the region
23
.
As stated previously, the timed etch process is used to etch through the bulk of the thickness of the initially formed layer of material from which the gate electrode
16
will be formed. However, at some point, it becomes necessary to use an endpoint etch process so that the underlying gate insulation layer
14
comprised of, for example, silicon dioxide, will not be consumed in completing the formation of the gate electrode
16
. This endpoint etch process may be performed in the region indicated by line
24
in FIG.
2
. Such endpoint etching processes often rely on optical emission spectrometry to determine when the process endpoint is reached. That is, by analyzing the outgassing of the etching process, it can be determined when substantially all of the polysilicon is consumed and/or when portions of the underlying gate insulation layer
14
are beginning to be consumed. At that point, the process is halted.
The endpoint etch process described above is normally highly selective with respect to the material of the gate insulation layer
14
, e.g., silicon dioxide. However, one drawback with respect to such an endpoint etching process is that it does not produce as vertical a sidewall as would otherwise be desired. That is, in the region
24
where this endpoint etch process is performed, the sidewalls
18
of the gate electrode
16
tend to flare, as indicated by line
20
in FIG.
2
. This flaring, while problematic in and of itself, can be accommodated in designing the semiconductor device. That is, knowing the amount of this flaring, the transistor may otherwise be designed such that it operates within a desired range of performance characteristics.
However, problems do arise when the incoming layer of material from which the gate electrode
16
will be formed is thicker or thinner than anticipated. For example, when the incoming layer of material is thicker than anticipated, performing a timed etch process based upon the anticipated thickness results in starting the endpoint etch process at a point higher above the surface
13
of the substrate
12
than would otherwise be desired, thereby producing a profile similar to that indicated by dashed lines
22
in FIG.
2
. Note that, in this situation, the flaring of the gate electrode
16
is greater than would otherwise be anticipated, thereby increasing the effective channel length of the device and producing a slower device. In the depicted embodiment, the channel length of the device would be increased by a magnitude that is approximately twice that of the dimension
29
indicated in FIG.
2
. Conversely, in situations where the incoming layer of material from which the gate electrode will be formed is thinner than anticipated, performing a timed etch process based upon the anticipated thickness of the layer may result, in the worst case, in consuming part of the underlying gate insulation layer
14
prior to beginning the endpoint etch process. Thus, variations in the thickness of the incoming layer used to form the gate electrode
16
may adversely impact device performance.
The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of controlling a gate etching process. In one illustrative embodiment, the method comprises forming a first layer comprised of a gate insulation material above a semiconducting substrate and forming a second layer of material above the layer of gate insulation material. The method further comprises sensing a thickness of the second layer of material, and adjusting, based upon the sensed thickness of the second layer of material, at least one parameter of an etching process to be performed on the second layer of material to define a gate electrode of a transistor, the etching process comprised of at least a timed etch process and an endpoint etch process. In one particularly illustrative embodiment, the layer of gate insulation material is comprised of silicon dioxide, and the layer from which the gate electrode will be formed is comprised of polysilicon.
REFERENCES:
patent: 6274503 (2001-08-01), Hsieh
Bonser Douglas J.
Bushman Scott G.
Hussey, Jr. James H.
Purdy Matthew
Advanced Micro Devices , Inc.
Chen Jack
Nguyen Tuan H.
Williams Morgan & Amerson P.C.
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