Control of PCI memory read behavior using memory read alias...

Details Control of PCI memory read behavior using memory read alias... Control of PCI memory read behavior using memory read alias...

2005-06-14

2010-02-02

Cleary, Thomas J (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S313000

Reexamination Certificate

active

07657690

ABSTRACT:
A method of controlling memory read behavior in PCI devices includes connecting a master PCI device to a PCI bus. The master PCI device is constructed and arranged to issue a Memory Read Line or a Memory Read Multiple initial command. A target PCI bridge device is connected to the PCI bus. The target PCI bridge device is constructed and arranged to prefetch data from host memory on behalf of the master PCI device and to store the prefetched data. A data transfer transaction is established between the master PCI device and the target PCI bridge device and prefetched data is stored at the target PCI bridge device. A bit is selectively preset in at least one of the PCI devices such that if a disconnect of the transaction occurs, the target PCI bridge device recognizes a subsequent request as a continuation of the initial request and sends prefetched data to the master PCI device.

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