Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1999-03-24
2001-11-13
Thai, Xuan M. (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S500000, C713S300000
Reexamination Certificate
active
06317840
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the field of integrated circuits, and more specifically relates to an integrated circuit, such as a microprocessor, which may include multiple equivalent functional units for power reduction purposes.
BACKGROUND OF THE INVENTION
There is increasingly a requirement in the design of modern integrated circuits to reduce power consumption such that applications that utilize battery power can operate for longer periods of time. For example, cellular phones, personal digital assistance, and lap tops, are all examples of battery-based systems that utilize integrated circuits. A primary consumer of power in such systems is the microprocessor, which is designed to deliver as much speed and performance as possible. Unfortunately, as a general rule, the speed of the microprocessor is proportional to the rate of power consumption. Thus, many systems include mechanisms to slow down the clock speed in the microprocessor to reduce power consumption during periods when high performance is not required. Other similar mechanisms place the microprocessor in a “sleep mode” that utilize low power, but must be woken up before operations can continue.
It is recognized in such systems that there arise occasions when the microprocessor must keep performing its operations, but not necessarily at the same speed (and therefore power rate) that is required during periods of peak performance. Thus, a mode of operation somewhere between “sleep mode” and normal high speed operations would adequately meet the system's requirements. For example, a personal digital assistant may not need to be operating at its full capacity until an input from the keyboard or screen is accepted. As noted, the current method of achieving such a reduction in central processing unit (CPU) power is by reducing the clock to the processor units. Complementary metal oxide semiconductor (CMOS) designs have a linear relationship between speed and power. Accordingly, reductions in the clock rate also reduce power consumption. However, the slowing down of the clock rate to most critical functional units (e.g., a multiplier circuit) does not reduce the total amount of energy required to complete an operation, it merely extends the period over which the energy is consumed. Thus, the same amount of energy will be used, just over a longer period of time. Therefore, slowing down the clock rate does not necessarily guarantee a reduction in the total power consumption required by the microprocessor.
It is recognized that power consumption is directly related to the amount of toggling of wires or nets within a circuit. Each time a wire toggles between a low and high voltage level, a certain amount of power is consumed. In most high speed functional circuits, the design emphasis is placed on speed, rather than power consumption. To achieve high speed functional circuits, numerous parallel operations need to be implemented simultaneously. Thus, any time a high speed functional operation is performed, a high number of toggles occur within a very short time period, consuming a tremendous amount of power. Moreover, because such operations utilize numerous parallel processes that require different amounts of time to complete their individual calculation, the output node of a parallel processing operation may toggle numerous times before a final result (i.e., a steady state) is reached. An example of this is depicted in
FIG. 3
, where an output signal
56
of a fast multiply circuit is depicted. It can be seen at reference numeral
60
that the output signal
56
toggles numerous times before reaching a steady state. From a functional standpoint, the toggling does not represent a problem so long as the steady state is reached before the end of the clock cycle
62
. Unfortunately, the unnecessary toggling
60
characterized in most high speed circuits consumes power and therefore drains the systems battery.
Accordingly, a solution for power reduction is needed even after the clock has been slowed to its lowest frequency. Without a processor that can deliver low power performance, battery powered applications cannot be fully exploited.
SUMMARY OF THE INVENTION
The invention provides a system for decreasing the power consumption of a microprocessor while maintaining its performance. The invention provides that for any given function in a processor, a second equivalent function can be implemented. In order to reduce power consumption, the second equivalent function may be implemented with a slower, less energy consuming circuit. Accordingly, the microprocessor is designed such that the second equivalent function is afforded more time to complete the same operation, or is designed to use a lower speed option available within the processor to minimize the number of additional cycles required. Accordingly, the invention comprises a processing system that comprises a first circuit for performing a function at a first, normal speed; a second circuit for performing the same function at a second, slower speed; and a control system for selecting either the first or second circuit to perform the function.
The processing system further comprises a mechanism for controlling the rate of execution of processor instructions. Specifically, because the amount of time to complete a function depends on which circuit the control system selects, the execution of subsequent processor instructions in the processor's pipeline may need to wait until the function is complete. Controlling the rate of execution may be accomplished by varying the clock speed to the pipeline, or by having the pipeline check with the control mechanism to determine if the function is complete. Finally, the decision to selecting either the normal speed circuit, or the functionally equivalent slower speed circuit can be controlled by either an opcode in the instruction stream, or by an external signal.
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patent: 5128890 (1992-07-01), Girardeau, Jr.
patent: 5426755 (1995-06-01), Yokouchi et al.
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patent: 5694349 (1997-12-01), Pal
patent: 5774701 (1998-06-01), Matsui et al.
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Dean Alvar A.
Goodnow Kenneth J.
Perry Patrick E.
Ventrone Sebastian T.
Chadurjian Mark F.
International Business Machines - Corporation
Schmeiser Olsen & Watts
Thai Xuan M.
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