Control of inputs to a memory device

Details Control of inputs to a memory device Control of inputs to a memory device

2007-03-05

2010-06-08

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189060, C365S193000, C365S226000, C365S229000, C365S233100

Reexamination Certificate

active

07733731

ABSTRACT:
A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

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