Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2001-12-18
2003-11-04
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S743000, C438S756000
Reexamination Certificate
active
06642121
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to fabrication techniques of integrated semiconductor devices and in particular to fabrication techniques of poly-emitter bipolar devices.
BACKGROUND OF THE INVENTION
Bipolar devices with doped polycrystalline silicon (polysilicon) emitters, commonly referred to as poly-emitter bipolar devices, and typically bipolar transistors, are very numerous in many integrated circuits designed for operating at radio frequency because they permit the formation of exceptionally shallow emitter junctions and of self aligned structures with modern fabrication techniques. Moreover, poly-emitter bipolar transistors provide for a higher switching speed and a higher current gain (HFE), in common emitter configuration, substantially without increasing the base resistance, than their counterparts with a more conventional structure.
It has been established that the higher current gain property is tied to the presence of a very thin layer of silicon oxide (one or few mono-layers) at the interface between the monocrystalline silicon of the emitter area of the semiconductor substrate and the polysilicon layer deposited on it. For example, see A. K. Kapoor and D. J. Roulston, “Polysilicon Emitter Bipolar Transistors”, 1989 IEEE Press.
Several physical models have been devised to describe such an interface oxide layer as a tunnel barrier for holes, so justifying the increment of the current gain when the base current decreases. Distribution diagrams of holes in a poly-emitter device are depicted in
FIG. 1
, while the holes distribution in the polysilicon layer is depicted in FIG.
2
.
In the case depicted in
FIGS. 1 and 2
, both the emitter resistance (RE) as well as the current gain (HFE) depend strongly by the barrier characteristics of the oxide film at the interface. In general RE and HFE are proportional to the expression:
ⅇ
A
δ
B
𝒳
wherein &dgr; and &khgr; represent respectively the thickness and the highness of the barrier and A and B are constants.
Naturally, for a standard thermal oxide, &khgr; is about 0.6 eV for electrons and 1.1 eV for holes, but, in the case of the oxide that is presumed to be present at the interface between the monocrystalline silicon and the polysilicon upon detecting a certain amount of oxygen, per unit area these values appear to be markedly depressed because of the non-stoichiometric form of such an interface oxide. For this reason, the trade-off between the RE and HFE values depends on the barrier property of the interface film of oxidized silicon though the HFE shows an increasingly marked increase upon an increase of the amount or “thickness” of the interface oxide (or more precisely of the concentration of oxygen atoms per unit area).
The main technical problem in fabricating this kind of integrated structure is represented by the difficulty of controlling the physical-chemical characteristics of the interface, in consideration of the commonly used techniques for depositing the polysilicon that typically are based on a low pressure chemical vapor deposition process (LPCVD). In poly-emitter bipolar devices, the presence at the interface of an amount of oxygen comprised between 1 and 2×10
15
oxygen atoms per cm
2
of interface area has been instrumentally measured by NRA (Nuclear Reaction Analysis).
The values of oxygen concentration at the interface, measured by the NRA technique, are reported in
FIG. 3
together with the measured values of HFE for different devices, in which the interface had been subjected to different process conditions. It can be seen clearly that the values of HFE depend strongly on the amount of oxygen at the interface and that even small differences produce remarkable variations of the current gain. To obtain acceptable HFE values (100±30), the oxygen concentration at the interface must be between 1 and 2×10
15
atoms/cm
2
.
Conventional fabrication processes may contemplate a treatment of the surface of the monocrystalline silicon in the emitter area with a diluted solution of hydrofluoric acid (commonly 1% by weight) before introducing the wafer in the polysilicon LPCVD reactor. Hydrogen passivation of the silicon surface by contacting it with hydrofluoric acid is effective in limiting a spontaneous re-oxidation of the silicon surface exposed to air at room temperature.
Nevertheless, during the loading of the wafer inside the heated chamber of the LPCVD reactor and while evacuating the reactor, the monocrystalline silicon surface oxidizes freely determining a wide dispersion of the values of the current gain of the transistors so fabricated. A typical LPCVD reactor is depicted in
FIG. 4. A
typical LPCVD process for depositing a layer of polysilicon is illustrated in a general manner in the following table, though conditions of each of the 14 phases may be slightly different, depending on the type of device being integrated and on the fabrication technology.
BOAT IN
BOAT = 60
35 cm/min
T = 620° C.
BOAT = 5
25 cm/min
BOAT IN
5 cm/min
H1 − N2 = ON
T1
t = 3 min
PRE-VACUUM
H GATE = ON
T2
t = 4 min
VACUUM
GATE V = ON
T3
t = 4 min
LEAK-CHECK
GATE V = OFF
T4
t = 30 s
VACUUM
GATE V = ON
T5
t = 30 min
TEMP-STAB 1
Low N2 = 200 sccm
CONTROL: TC SPIKE
(flux measure)
N2 dil = 200 scm
T6
t = 30 min
TEMP-STAB 2
Low N2 = 200 sccm
CONTROL: TC SPIKE
N2 dil = 200 scm
T7
t = 4 s
PRE-DEP
SiH4 US = OFF
SiH4 D = 36 sccm
SiH4 I = 44 sccm
N2 dil = 200 scm
T8
t = 40 min
DEPOSITION
SiH4 US = ON
SiH4 D = 36 sccm
SiH4 I = 44 sccm
N2 dil = 200 scm
T9
t = 100 s
POST DEP
SiH4 US = OFF
SiH4 D = 0 sccm
SiH4 I = 0 sccm
N2 dil = 200 scm
T10
t = 5 min
PURGE
Low N2 = 200 sccm
N2 dil = 25O scm
HOLD
MANUAL START
Low N2 = 200 sccm
N2 dil = 250 scm
T11
t = 13 min
VENT
N2 = 5 slm
BOAT OUT
H1 − N2 = ON
BOAT = 25 cm/min
To limit oxidation of the monocrystalline silicon surface during the loading inside the heated chamber of the reactor and during evacuation of the chamber, a common practice is to maintain the wafer in an atmosphere of inert gas, such as nitrogen (N
2
), helium or argon during loading and evacuation. By introducing nitrogen (N
2
) the availability of oxygen or of any other oxidant in the atmosphere inside the reactor may be greatly reduced thus preventing excessive oxidation of the silicon while heating up to the chamber's temperature. This well known technique for reducing the concentration of oxidant inside the chamber of the LPCVD reactor and eventually of the chamber's temperature when loading the wafers, tends to produce excessively low gain values of the transistors.
To overcome this drawback, it has been proposed to “condition” the surface of the monocrystalline silicon wafer, before introducing it in the LPCVD reactor for depositing the polysilicon, by chemically oxidizing the silicon surface previously passivated by treatment with hydrofluoric acid, using hydrogen peroxide (H
2
O
2
). This technique, even if it ensures the presence of an adequate amount of native oxide at the interface between the monocrystalline silicon and the polysilicon layer, produces an excessive dispersion of the current gain values (HFE).
Moreover, the pre-oxidation treatment with H
2
O
2
requires sophisticated control devices because of the remarkable reactivity of silicon even at low temperature. In fact, even if a residual hydrogen passivation of the surface of the monocrystalline silicon may be still found up to a temperature of about 300° C., it has been demonstrated that silicon begins to oxidize well before hydrogen passivation of its surface has completely disappeared.
A thermal oxidation pre-treatment in presence of oxygen and/or steam of the monocrystalline silicon surface to prevent an uncontrolled oxidation during loading, heating and evacuati
Cali′ Denise
Camalleri Cateno M.
Ferla Giuseppe
Lorenti Simona
Vasquez Patrizia
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chaudhuri Olik
Garcia Joannie Adelle
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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