Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-05-17
2004-05-25
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C710S120000
Reexamination Certificate
active
06742087
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of controlling access to independently controllable memory units commonly shared by data processing units and an access controlling unit including independently controllable memory units commonly shared by data processing units.
2. Description of the Prior Art
An access controlling unit controlling access from a data processing unit to a memory unit in another data processing unit coupled to the data processing unit through a buffer is known. Such a prior method is disclosed in Japanese patent application provisional publication No.5-289987. Another access controlling unit controlling access to a resource commonly shared by data processing units through a common bus and buffers provided to data processing unit is known. Such a prior art access controlling unit is disclosed in Japanese patent application provisional publication No. 3-75959. In this prior art access controlling unit, the data processing unit that has obtained the right to use the common bus can access the shared resource.
In the case of the former access controlling unit, when one data processing unit accesses the shared memory unit, another data processing unit is stopped. Thus, if access to the shared memory unit is frequent, the processing efficiency will decrease.
In the case of the latter access controlling unit, either of the data processing units is stopped only when both data processing units require the common bus at the same time. Thus, the processing efficiency is higher than that of the former data processing unit. However, if it is assumed that there is more than one common resource, though both data processing units access different resources at the same time, the data processing unit without the right to use the common bus is stopped.
In the case of the latter access controlling unit, either of data processing unit is stopped only when both data processing unit require the right of using the common bus at the same time. Thus, the processing efficiency is higher than that of the former data processing unit. However, if it is assumed that there are more than one common resources. Though both data processing units access to different resources at the same time, the data processing unit without right of using the common bus is stopped.
Still another prior art access controlling unit coupled to memory units and data processing unit is known, wherein different data processing units can access different memory units, respectively.
FIG. 15
is a block diagram of such a prior art access controlling unit. A control unit
100
for coupling data busses DX and DY from two data processing units X and Y to data buses DA and DB from two memory units A and B is provided as the access controlling unit.
In this example, the data buses DX, DY, DA, and DB have the same bus width (sixteen bits), and the memory units A and B have continuously changing addresses, respectively.
The control unit
100
includes a data path control circuit
110
. The data path control circuit
110
includes an X-side loading path unit
111
for coupling either of the data bus DA or DB to the data bus DX in response to the path control signal Sx, a Y-side loading path unit
112
for coupling either of the data bus DA or DB to the data bus DY in response to the path control signal Sy, an A-side storing path unit
113
for coupling either of the data bus OX or DY to the data bus DA in response to the path control signal Sa, and a Y-side storing path unit
114
for coupling either of the data bus DX or DY to the data bus DB in response to the path control signal Sb.
Here, each of the path units
111
to
114
includes a gate circuit having a ti-state buffer, so that turning on the gate circuit enables loading and storing in each of path units
111
to
114
. The control unit
100
further includes a control circuit (not shown) for generating the path control signals Sx, Sy, Sa, and Sb in accordance with address signals and various control signals outputted by the data processing units X and Y.
The control circuit discriminates access from each of the data processing units X and Y among to-A-side access, to-B-side access, and no access on the basis of the address, and various control signals from the data processing units X and Y. Next, the control circuit effects the arbitration process for every data processing unit as shown by a flow chart as shown in FIG.
16
A.
Here, the data processing units operate synchronously with each other and execute one process at every processing cycle, for example, one clock cycle. Thus, it is assumed that the arbitration process mentioned below is executed at every processing cycle.
When the arbitration process is activated, the control circuit judges whether there is no access in step S
510
. If there is no access in step S
510
, processing ends. If there is access, the control circuit judges whether there is collision in step S
520
. If there is no collision, the control circuit permits the access in step S
540
.
Comparing the destinations of accesses from the data processing units X and Y provides this judgment. If the destinations are the same, there is collision as shown by the table in FIG.
16
B.
If there is collision, the control circuit judges which access has higher priority in step S
530
. The control circuit permits the access from the data processing unit having a higher priority and inhibits the access from the data processing unit having a low priority in steps S
540
and S
550
.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a superior method of controlling access to memory units and a superior access controlling unit.
According to the present invention, a first aspect of the present invention provides a method of controlling access to a memory device commonly shared by a plurality of data processing units, said memory device including 2
M
memory units (M being a natural number) which are independently controllable and have the same data bus width as said data processing units, comprising steps of: (a) assigning addresses to each of said memory units such that addresses in each of said memory units change in the same manner as other memory units and corresponding addresses in said memory units vary in accordance with arrangement of said memory units in said memory device; (b) when one of said data processing units requests to read data in said memory device at a data size which is 2
k
times said data bus width (1≦k≦M and k being a natural number), reading (loading) said data from the corresponding 2
k
memory units at the same time; and (c) independently supplying each of data from said corresponding 2
k
memory units 2
k
times to said one of said data processing units.
According to the present invention, a second aspect of the present invention provides a method based on the first aspect, wherein in step (b), when said one of said data processing unit requests reading (loading) desired data at a desired address at a data size which is 2
P
times said data bus width (0≦p≦M−1 and p being a natural number), and if any other data processing unit does not request access to said memory device, reading (loading) another data at an address following to said desired address from data processing units other than said one of said data processing units and storing other data in a temporary register as pre-loading data; and after supplying said desired data to said one of said data processing units, when said one of data processing unit requests reading (loading) with an address agreeing with said address, supplying said other data from said temporary register to said one of said data processing units.
According to the present invention, a third aspect of the present invention provides a method based on the second aspect, wherein, when said desired data is other than an instruction for executing a predetermined process in said one of said data processing units, inhibiting reading of said other data.
According to the present invention, a third aspect of the present invention
Hayakawa Hiroshi
Ishihara Hideaki
Denso Corporation
McLean-Mayo Kimberly
Posz & Bethards, PLC
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