Control method of semiconductor memory device and...

Details Control method of semiconductor memory device and... Control method of semiconductor memory device and...

2006-11-28

2006-11-28

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S230060, C365S239000, C365S204000, C365S203000

Reexamination Certificate

active

07142468

ABSTRACT:
It is intended to provide a control method of a semiconductor memory device and a semiconductor memory device capable of shortening pre-charge operation time that comes after termination of successive data access operation, namely, successive data read/write operation, without causing deterioration of restore voltage to memory cells and delay of initial data access time. An activated word line WL0is deactivated with appropriate timing that is between time after bit line pairs (BL0and /BL0, . . . BLN and /BLN) are differentially amplified up to full amplitude voltage level and time where column selecting lines CL0, . . . CLN are selected. That is, deactivation time τA for the word line can be embedded in a period of successive data access operation. Pre-charge operation can be terminated within time that is a sum of deactivation time τB of a sense amplifier and equalizing time τC of the bit line pairs. Thereby, pre-charge period can be shortened.

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