Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-04-12
2005-04-12
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185090, C365S185290, C365S185330
Reexamination Certificate
active
06879528
ABSTRACT:
A control method of nonvolatile memory is provided, wherein it does not happen that data which ought to have been erased are not erased, or data which ought to have been written are lost even if a forced interruption takes place due to shutdown of a power source for a memory device, a reset command, or the like occurs when data are written in a last page of a block, the block is validated by setting the block data validation flag provided in the redundant area of the last page of block 0 (valid). Furthermore, a counter judges whether the data is new or old, and data can be protected even if the above-mentioned solution cannot be implemented.
REFERENCES:
patent: 5978273 (1999-11-01), Shigemura
patent: 6421279 (2002-07-01), Tobita et al.
patent: 5-216780 (1993-08-01), None
patent: 11282765 (1999-10-01), None
patent: 2000-330850 (2000-11-01), None
Iwata Kazuya
Kogita Shigekazu
Takeuchi Akio
Akin Gump Strauss Hauer & Feld L.L.P.
Le Vu A.
Luu Pho M.
Matsushita Electric - Industrial Co., Ltd.
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