Control method for error detection & correction...

Details Control method for error detection & correction... Control method for error detection & correction...

2005-09-29

2009-06-02

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S755000, C702S189000, C379S399020

Reexamination Certificate

active

07543220

ABSTRACT:
The present invention provides a control method for an error detection & correction apparatus, comprising a plurality of data processing apparatuses which reside in a data communications path and partake in exchanging data by the unit of error correcting code, and a plurality of information exchange paths which are installed between the plurality of data processing apparatuses; and generating a true syndrome by exchanging a partial syndrome relating to a part of the data partaken by each of the data processing apparatuses by way of the information exchange paths, comprising the step of exchanging renewal information relating to a part of the data partaken by each of the data processing apparatuses with the other data processing apparatus by way of the information exchange path.

REFERENCES:
patent: 4736376 (1988-04-01), Stiffler
patent: 5768294 (1998-06-01), Chen et al.
patent: 2002/0152444 (2002-10-01), Chen et al.
patent: 57-152599 (1982-09-01), None
patent: 4-023048 (1992-01-01), None
patent: 11-232129 (1999-08-01), None
NN84046142: ‘Fault-Tolerant Memory With Single Error Correcting Codes,’ IBM Technical Disclosure Bulletin, vol. No. 26;Issue No. 11;p. No. 6142-6144;Apr. 1, 1984.

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