Control for timed access of devices to a system bus

Details Control for timed access of devices to a system bus Control for timed access of devices to a system bus

1999-01-19

2002-12-10

Lefkowitz, Sumati (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S025000, C710S028000, C713S400000

Reexamination Certificate

active

06493775

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus control device, and in particular to a bus control device which enables a plurality of devices such as processors and DMAC's (Direct Memory Access Controllers) which can be a bus master to access a system bus.
In recent years, the performance of a serial processing computer is going to approach the physical limits. As one solution for further improving the performance of a computer, a multi-processor system has been proposed. In this system, how effectively the bus control device utilizes the system bus is important.
2. Description of the Related Art
FIG. 11
illustrates an arrangement of a general bus control device, in which to an address bus
21
, a data bus
22
, and a control bus
23
forming a system bus
20
, are connected processors (hereinafter occasionally referred to as MPU's)
10
a
and
10
b
, a DMAC
11
, a memory
12
, and processing circuits (hereinafter occasionally referred to as I/O's (Input/Output circuits))
13
a
and
13
b.
It is to be noted that
FIG. 11
does not show a usual system bus controller for the MPU
10
a
, the MPU
10
b
, the DMAC
11
, the memory
12
, the I/O
13
a
, and the I/O
13
b.
FIG. 12
illustrates a timing sequence of the MPU
10
a
accessing the system bus
20
, namely, a read cycle of the MPU
10
a
in which the MPU
10
a
reads data from the memory
12
and a write cycle in which the-MPU
10
a
writes data in the memory
12
.
The bus control device in its entirety synchronizes with a bus clock
101
, while the MPU
10
a
synchronizes with a clock
201
which is made by dividing the frequency of the bus clock
101
into the half.
In the read cycle, the MPU
10
a
outputs an address signal
202
at the fall of the clock
201
(at timing t
41
) and activates a memory read signal
203
(negative-true logic) at the subsequent rise of the clock
201
(at timing t
42
). A system bus controller of the MPU
10
a
, having received the address signal
202
and the memory read signal
203
, activates an MPU
10
a
-bus request signal
102
(negative-true logic) at the subsequent rise of the bus clock
101
(at timing t
43
).
Upon receiving this request signal
102
, the system bus first confirms that the address bus
21
and the data bus
22
are accessible, and then activates an MPU
10
a
-bus acknowledge signal
103
(negative-true logic) at the subsequent fall of the clock
101
(at timing t
44
). Having received this bus acknowledge signal
103
, the system bus controller of the MPU
10
a
outputs the address signal
202
and the memory read signal
203
to the address bus
21
and the control bus
23
respectively.
Receiving the address signal
202
and the memory read signal
203
from the address bus
21
and the control bus
23
respectively, the memory
12
outputs a data signal
208
designated by the address signal
202
to the data bus
22
. When the data signal
208
become effective on the data bus
22
(at timing t
45
), the system bus controller of the MPU
10
a
outputs a ready signal
207
notified by the memory
12
to the MPU
10
a
. The MPU
10
a
reads the data, completes the read cycle, and then releases the system bus (at timing t
46
).
In the write cycle, the MPU
10
a
outputs the address signal
202
at the fall of the clock
201
(at timing t
51
), and without activating the memory read signal
203
, outputs a data signal (not shown in
FIG. 12
) at the subsequent rise of the clock
201
(at timing t
52
). As in the read cycle, the system bus controller of the MPU
10
a
, after having made a bus request with the bus request signal
102
(at timing t
53
), receives the bus acknowledge signal
103
. Having received this bus acknowledge signal
103
, the system bus controller outputs the address signal
202
to the address bus
21
and outputs the said data to the data bus
22
as the data bus signal
208
.
The system bus controller of the MPU
10
a
outputs a memory write signal
204
to the control bus
23
(at timing t
55
). Having received this memory write signal
204
, the memory
12
has the data signal
208
designated by the data bus
22
written in the address designated by the address signal
202
on the address bus
21
. The system bus controller, after having completed writing data to the memory
12
, outputs the ready signal
207
notified by the memory
12
to the MPU
10
a
(at timing t
56
). The MPU
10
a
completes the write cycle and releases the system bus (at timing t
57
).
FIG. 13
illustrates a timing sequence for the DMAC
11
to access the system bus
20
, namely, a read and a write cycle for the DMAC
11
to read data from the memory
12
to write the data in the I/O
13
a
and to write the data read from the I/O
13
a
in the memory
12
, respectively.
As in
FIG. 12
, the bus control device in its entirety synchronizes with the bus clock
101
, while the DMAC
11
synchronizes with the clock
201
which is made by dividing the frequency of the bus clock
101
into the half.
In the read cycle, the DMAC
11
outputs the address signal
202
at the fall of the clock
201
(at timing t
61
) and activates-the memory read signal
203
(negative-true logic) at the ;subsequent rise of the clock
201
(at timing t
62
). A system bus controller of the DMAC
11
transmits/receives a DMAC-bus request signal
102
(hereinafter a hyphen “-” indicates that the latter is used for the former) and a DMAC-bus acknowledge signal
103
to/from the system bus, and acquires a use (right for use) of the system bus (at timings t
63
, t
64
). Then the system bus controller of the DMAC
11
outputs the address signal
202
and the memory read signal
203
to the address bus
21
and the control bus
23
respectively.
Receiving the address signal
202
and the memory read signal
203
from the address bus
21
and the control bus
23
respectively, the memory
12
outputs the data signal
208
designated by the address signal
202
to he data bus
22
. At the subsequent rise of the clock
201
(at timing t
65
), he DMAC
11
outputs an I/O write signal
206
.
When the data signal
208
become effective on the data bus
22
, the I/O
13
a
, having received the I/O write signal
206
, reads the data signal
202
on the data bus
22
. The system bus controller of the DMAC
11
outputs the ready signal
207
notified by the memory
12
(at timing t
66
). The DMAC
11
completes the read cycle and releases the system bus (at timing t
67
).
In the write cycle, the operations at the timings t
71
~t
74
are the same as the read cycle except that at at timing t
72
, the DMAC
11
activates an I/O read signal
205
instead of activating the memory read signal
203
. At timing t
74
, having acquired a use of the system bus, the system bus controller of the DMAC
11
outputs the address signal
202
and the I/O read signal
205
to the address bus
21
and the data bus
23
, respectively.
Upon receiving the I/O read signal
205
, the I/O
13
a
outputs the data signal
208
to the data bus
22
. At the subsequent rise of the clock
201
(at timing t
75
), the DMAC
11
outputs a memory write signal
204
. In response to this signal, the memory
12
has the address signal
202
on the address bus
21
to read in the data signal
208
on the data bus
23
.
At the end of the reading operation in view of the memory access time (at timing t
76
), the system bus controller of the DMAC
11
outputs the ready signal
207
notified by the memory
12
to the DMAC
11
. Then the DMAC
11
completes the write cycle and releases the system bus (at timing t
77
).
In such a prior art bus control device, any one of the MPU
10
a
, the MPU
10
b
and the DMAC
11
executes the process as a bus master. This bus master occupies the system bus
20
from the beginning to the end of the cycle time for accessing the memory
12
or the I/O's
13
a
,
13
b.
Therefore, the MPU or the DMAC other than the bus master has to wait until the bus master completes the cycle time and releases the system bus
20
because no acknowledge signal is ret

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