Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-03-10
2003-11-04
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C714S055000
Reexamination Certificate
active
06643734
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a control device and control method for a disk array used in a computer system, more particularly, to a control device and control method for a disk array which changes the operation monitoring time for data write or read of a disk array based on the state of the disk array.
A conventional disk array known as a Redundant Array of Independent (or Inexpensive) Disks (RAID) system uses a plurality of inexpensive disk devices which operate independently from each other and also which are connected in parallel. The RAID system stores data dispersed to the small capacity disk devices, and accesses the dispersed stored data in parallel and at the same time. Therefore, the RAID system can process an Input/Output (I/O) request at high speed and efficiently.
There are six classifications from level 0 to 5 in the RAID. The classifications are described in detail, for example, in the publication William Stallings, “Computer Organization and Architecture”, Prentice-Hall International Inc., Fourth Edition, 1996, pages 161-169.
The disk array of RAID level 3 or 5 has one or a plurality of disk groups called a parity group, and each parity group includes a plurality of data disk devices for storing data and one redundant disk device for storing parity data. For simplicity, it is assumed that the disk array has one parity group and the parity group includes (N−1) data disk devices and a single redundant disk device (i.e., a total of N).
Write data transferred to a disk array controller from a data processor is divided into a plurality of (N−1) of data in the disk array controller (in bit or byte units). Parity data for one parity group is formed from divided plurality of data. The disk array controller writes the (N−1) divided data into corresponding (N−1) data disk devices and the parity data into the redundant disk device in parallel. At this time, after successful access to the (N−1) disk devices in the data disk devices and the redundant disk device, the disk array controller reports to the data processor that the data write has completed.
On the other hand, when a data read request is transferred from the data processor to the disk array controller, if the disk array controller successfully accesses the corresponding addresses of the (N−1) disk devices, the requested data can be constructed (synthesized) from the data of the (N−1) disk devices. Therefore, the disk array controller can report to the data processor that the data read has completed and transfer the synthesized data to the data processor.
The technique in which the disk array controller reports to the data processor that the accesses have completed when the accesses to the disk array associated with the data write and data read operations described above are completed (successful) for the (N−1) disk devices, is disclosed, for example, in Japanese Patent Application No. Hei 7-200191. In addition, related techniques are also disclosed in Japanese Patent Applications No. Hei 8-123628 and No. Hei 8-171463.
As described above, when all the disks (N sets) constituting a parity group are operating normally, the disk array controller can respond to the data processor if data write/read operations are completed for the arbitrary (N−1) of the N disk devices.
When all the disk devices are operating normally, the data processing for data write/read operations, for example, will be completed within about 10 to 30 milliseconds when there is a small amount of data, e.g. 32 kilobytes, and about 20 to 40 milliseconds when there is a large amount of image data, e.g. 400 kilobytes. Therefore, even if there is a problem (the problem does not mean failure of disk device) in one disk device in N disk devices, when the data write operation is being performed, there is enough time for re-trying access to the disk device for correcting an error after the data processor is notified of the completion of the data write. On the other hand, when the data read operation is being performed, there is also enough time for retrying access to the disk device for correcting an error after the read data are transferred to the data processor.
Consequently, when all the disk devices comprising a parity group are operating normally, even if the monitoring time for the inability (failure) of data write/read operations is set for 10 seconds, because the data write/read operation for arbitrary (N−1) in N disk devices, as mentioned above, would usually be completed in a short time, neither notification of completion of a data write operation nor data transfer (in a case of a reading operation) to the data processor would be greatly delayed. That is, the data processor can transfer the subsequent data write/read request to the disk array controller immediately after it has received the notification for completion of data write operation or the data read out from the disk array controller.
However, when there is a reduced state in which one of the disk devices constituting a parity group can not be used because of a failure, data processing is not completed unless the data write/read operations for all of the (N−1) disk devices, except for a defective disk device, has been successful. In this situation, if one set in the (N−1) disk devices, except the defective disk device, has a problem and also the monitoring time for the inability (failure) of data write/read operations is set, for example, at 10 seconds of the same time as that of the normal condition of the parity group, the disk array controller, in a worst case, reports to the processor that the access has failed after re-trying access for error correction for 10 seconds. This creates a problem because the data processing speed of the entire computer system decreases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a control device and control method for a disk array which changes the operation monitoring time of a data write or read of a disk array based on the state of the disk array.
Another object of the present invention is to provide a control device and control method for a disk array which sets the access re-trying time for error correction as short as possible when one of the disk devices constituting a parity group can not be used because of a failure, and reports to the processor its result as fast as possible when the access re-trying for error correction does not complete within the re-trying time.
According to one aspect of the present invention, a control device for a disk array is provided which comprises: a first element which accesses a plurality of disks of the disk array; a timer which counts to a first timeout value when all of the disks are normal and to a second timeout value when one of the disks is defective, unless the first element receives a response from the disks; and a second element which determines that an access fails if the timer reaches one of the first or second timeout values.
According to another aspect of the present invention, a control device for a disk array is provided which comprises: a first element which monitors an operation of the disk array for a predetermined time; and a second element which changes the predetermined time based on a state of the disk array.
According to another aspect of the present invention, a control method for a disk array is provided which comprises: accessing a plurality of disks of the disk array; counting to a first timeout value when all of the disks are normal and to a second timeout value when one of the disks is defective, unless there is a response during the accessing step; and determining that an access fails if one of the first or second timeout values is reached during the counting step.
REFERENCES:
patent: 5530872 (1996-06-01), Smeltzer et al.
patent: 5758057 (1998-05-01), Baba et al.
patent: H9-69027 (1995-03-01), None
patent: 7-200191 (1995-08-01), None
patent: H7-281966 (1995-10-01), None
patent: 8-123628 (1996-05-01), None
patent: 8-171463 (1996-07-01), None
William S
Kikuchi Yoshihide
Mabuchi Atsushi
Kim Matthew
NEC Corporation
Sughrue & Mion, PLLC
Tran Denise
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