Control component for controlling a delay interval within a...

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S193000, C365S239000

Reexamination Certificate

active

08059476

ABSTRACT:
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

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