Control circuits comparing index offset and way for cache...

Details Control circuits comparing index offset and way for cache... Control circuits comparing index offset and way for cache...

2005-02-22

2005-02-22

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S167000

Reexamination Certificate

active

06859860

ABSTRACT:
A circuit for controlling a cache system having a store queue having plural stages for storing store instructions. The circuit includes: a first comparator circuit for comparing, in view of index and off-set, an instruction with tag-retrieval to the store instructions stored in the store queue; and a stalling circuit for selectively stalling the instruction with tag-retrieval if the instruction with tag-retrieval corresponds, in view of not only index but also off-set, to at least one of the store instructions.

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