Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2008-07-01
2008-07-01
Peugh, Brian P. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S153000
Reexamination Certificate
active
11446553
ABSTRACT:
A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for detecting that a first instruction intended for a first area is a predetermined instruction to be followed by a period during which the first area can receive no other instruction, and third circuitry for, during the period, providing instructions to another memory area.
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Burd, “Systems Architecture”, © 1998 Course Technology, 2ndedition, p. 166, 169, 204.
Chauvet Pascal
Marty Pierre
Rey Gaelle
Jorgenson Lisa K.
Morris James H.
Peugh Brian P.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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