Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2009-06-29
2011-11-22
Luu, Pho M (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S189040, C365S189050, C365S230080
Reexamination Certificate
active
08064277
ABSTRACT:
A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line driver by receiving a sensing-enable signal ‘IOSTB’, and to generate and output a second delay signal to a second global input/output line driver by receiving the sensing-enable signal. The first delay unit generates the second delay signal by delaying the sensing-enable signal in synchronization with a clock. The semiconductor memory apparatus also includes a second delay unit configured to generate a pipe latch control signal in response to the first delay signal and the second delay signal.
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Hynix / Semiconductor Inc.
Ladas & Parry LLP
Luu Pho M
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