Control circuit for EEPROM

Details Control circuit for EEPROM Control circuit for EEPROM

1990-01-26

1990-12-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

36518901, 36523006, 365149, G11C 1300

Patent

active

049775430

ABSTRACT:
A control circuit generating a write/erase high voltage pulse for an EEPROM is disclosed. The control circuit comprises a low frequency clock pulse oscillation circuit, a voltage booster circuit having at least 19 FET booster stages and a high voltage shaping switch circuit having an exponential rising pulse edge driven by the clock pulse.

REFERENCES:
patent: 4326134 (1982-04-01), Owen et al.
patent: 4488060 (1984-12-01), Simko
patent: 4648076 (1987-03-01), Schrenk
patent: 4805151 (1989-02-01), Terada
patent: 4907202 (1990-03-01), Kouzi
Yuji Yatsuda, Takaaki Hagiwara, Shin-ichi Minami, "A Byte Erasable 5V-Only 64 Kbit EEPROM", 433 Electronics & Communications in Japan 67 (1984), May.
Duane H. Oto, Vinod K. Dham, Keith H. Gudger, Michael J. Reitsma, Geoffrey S. Gongwer, Yaw Wen Hu, Jay F. Olund, H. Stanley Jones, Jr. and Sidney T. K. Nieh, "High-Voltage Regulation and Process Considerations for High-Density 5 V-Only E2PROM's", IEEE Journal of Solid-State Circuits, vol. SC-18 (1983), Oct. No. 5.

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