Control circuit for controlling on-die termination impedance

Details Control circuit for controlling on-die termination impedance Control circuit for controlling on-die termination impedance

2007-12-28

2009-12-08

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C365S222000

Reexamination Certificate

active

07629811

ABSTRACT:
The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal.

REFERENCES:
patent: 2004/0240298 (2004-12-01), Jin
patent: 2005/0134304 (2005-06-01), Lee
patent: 2005/0180229 (2005-08-01), Jin
patent: 2007/0126468 (2007-06-01), Kim
patent: 2008/0191734 (2008-08-01), Yang et al.
patent: 2009/0016124 (2009-01-01), Kim
patent: 1020050081315 (2005-08-01), None
patent: 1020070036635 (2007-04-01), None

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