Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1999-07-09
2000-12-26
Phan, Trong
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 94, H03K 1900
Patent
active
061665649
ABSTRACT:
A control circuit for clock enable staging between first and second clock macros wherein each clock macro produces a clock signal at an output in response to a transition of a global clock signal when an enable signal has been activated. The control circuit comprises a latch element having a first input coupled to the output of the first clock macro, a second input of the latch element is coupled to the output of the second clock macro, and an output node coupled to the enable input of the second clock macro. The output node of the latch element activates the enable input of the second clock macro responsive to the clock signal at the output of the first clock macro, and inactivates the enable input of the second clock macro responsive to the clock signal at the output of the second clock macro.
REFERENCES:
patent: 5151623 (1992-09-01), Agrawal
patent: 5939898 (1999-08-01), Henkel et al.
patent: 6005416 (1999-12-01), Beakes et al.
Intel Corporation
Phan Trong
LandOfFree
Control circuit for clock enable staging does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Control circuit for clock enable staging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control circuit for clock enable staging will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-999101