Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-06-07
2001-04-24
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S202000, C365S203000, C327S536000
Reexamination Certificate
active
06222782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor memory, and more particularly, to a control circuit for a bit line equalization signal in the semiconductor memory which equalizes each initial voltage at a bit line and bit bar line.
2. Discussion of Related Art
Bit lines and bit bar lines (also known as complementary bit lines) in semiconductor devices are data signal transferring paths directly connected to memory cells. Data signals are carried to the memory cells, or other data signals read from memory cells, are transferred to a sense amplifier through the bit lines and bit bar lines.
When a data signal is applied to one of the bit line pair (i.e., a bit line and corresponding bit bar line), a voltage difference between the bit line and the bit bar line is generated. The sense amplifier amplifies the voltage difference before transfer to a data bus. Capacitance of a capacitor in a memory cell is usually designed to be small for fast operation and low power consumption so that the voltage difference between the bit line and bit bar line is minute. Therefore, the initial voltage levels of the bit line and bit bar line should be equalized very precisely.
FIG. 1
shows a schematic circuit of a cell array and a sense amplifier which are electrically connected. Referring to
FIG. 1
, a bit line equalization circuit
102
, a memory cell
104
, and a sense amplifier
106
are connected to a bit line pair BL and /BL. A sense amplifier driver
108
is connected to the sense amplifier
106
.
In the bit line equalization circuit
102
, when a bit line equalization signal BLEQ becomes high, NMOS transistors
110
,
112
, and
114
all turn on, equalizing both the bit line BL and bit bar line /BL to a precharge voltage VBLP. Once the bit line equalization signal BLEQ drops down to a low level, the NMOS transistors
110
,
112
, and
114
all turn off. Thus, the bit line BL and bit bar line /BL maintain the precharge voltage level, in a floating state.
During this floating state, when a word line WL is activated to turn on an NMOS transistor
116
in the memory cell
104
, electric charge transfer occurs between the bit line BL and a cell capacitor
118
. Then, the sense amplifier
106
amplifies the resulting voltage difference between the bit line BL and bit bar line /BL. In this case, the voltage amplified by the sense amplifier depends on a PMOS gate voltage CSP and NMOS gate voltage CSN provided by a sense amplifier driver
108
. The PMOS gate voltage CSP and the NMOS gate voltage CSN operate as power source voltage and ground voltage, respectively, for the sense amplifier
106
.
FIG. 2
shows a bit line equalization signal generator in a semiconductor memory according to a related art. Referring to
FIG. 2
, a bit line enabling signal BLEIN comes from a mat selection signal. This signal is buffered by buffer
202
to produce a bit line equalization signal BLEQ having VDD and VSS signal levels (where VDD is the upper power supply voltage and VSS is the lower power supply voltage).
Recently, power supply voltages VDD of semiconductor memories have decreased from 5V, to 3.3V, to 2.5V. When 5V semiconductor memory design is transformed to that of 3.3V, or 3.3 to 2.5V, the voltage level of the bit line equalization signal BLEQ is also reduced due to the decreased power source voltage (i.e., 3.3V or 2.5V). Unfortunately, such bit line equalization signal BLEQ fails to provide sufficient driving force.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a control circuit for a bit line equalization signal in a semiconductor memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
One object of the present invention is to provide a control circuit for a bit line equalization signal in a semiconductor memory which has sufficient driving force by securing a bit line equalization signal of a high voltage level even if power voltage level is reduced.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a control circuit for controlling a bit line equalization signal in a semiconductor memory, including a level shifting portion to receive a bit line equalization signal having a voltage of VDD and to selectively raise the voltage of the bit line equalization signal above VDD, and a control portion to receive the bit line equalization signal and produce a control signal to cause the level shifting portion to raise the voltage of the bit line equalization signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5499218 (1996-03-01), Ahn et al.
patent: 5563831 (1996-10-01), Ting
patent: 5828611 (1998-10-01), Kaneko et al.
patent: 5828614 (1998-10-01), Gradinariu
Hyundai Electronics Industries Co,. Ltd.
Mai Son
LandOfFree
Control circuit for a bit line equalization signal in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Control circuit for a bit line equalization signal in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control circuit for a bit line equalization signal in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2445649