Control circuit and semiconductor memory device

Details Control circuit and semiconductor memory device Control circuit and semiconductor memory device

2002-01-03

2003-06-10

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000, C365S189050

Reexamination Certificate

active

06577550

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a control circuit that controls an internal circuit based on an external operation request and an internal operation request and to a semiconductor memory device including such control circuit.
Nowadays, a dynamic random access memory (DRAM), which has a large memory capacity, is used in electronic information devices. A DRAM is provided with a self-refresh function that refreshes cell data of a memory cell based on a counter operation of an internal circuit. A DRAM provided with the self-refresh function does not require an external refresh manipulation. Thus, power consumption is reduced and the designing of a circuit about the DRAM is facilitated.
FIG. 1
is a block circuit diagram illustrating a prior art input circuit section of a DRAM
100
, which is provided with a self-refresh function.
The DRAM
100
receives an output enable signal /OE, a write enable signal /WE, and a chip enable signal /CE
1
, which are all control signals. The signals /OE, /WE, /CE
1
are provided to filters
14
,
15
,
16
via input buffers
11
,
12
,
13
, respectively. Each of the input buffers
11
-
13
is an input initial stage circuit that coverts an input signal to a signal having a level corresponding to an internal voltage of a device and is, for example, a CMOS inverter circuit or a C/M (current mirror) differential amplification circuit.
Each of the filters
14
-
16
eliminates noise components, such as a glitch, from the signal provided by an external circuit. The data of the DRAM is held using a charge holding technique. When an undetermined noise is included in the input signal, the level of a word line is shifted in a state in which the internal operation of a device has not yet been determined. The elimination of a noise component prevents the data of a memory cell from being damaged.
The noise status of each signal changes in accordance with a system board, in which the DRAM
100
is used. Thus, the filters
14
-
16
are normally designed to resist noises that may be produced in the worst cases. Accordingly, the set value of the filters
14
-
16
normally restricts the access time for reading and writing data. Thus, the set value significantly affects the access time.
Output signals oeb
5
z, web
5
z, clb
5
z of the filters
14
,
15
,
16
are provided to first, second, and third control transition detectors (CTDs)
17
,
18
,
19
and to a control data decoder (CTLDEC)
20
. The transition detectors
17
,
18
,
19
each detect the transition of the status of the input signal and generates detection signals oerex, werex, cerex.
The control decoder
20
decodes commands based on the voltage level (high level or low level) of the external control signals (in this example, the chip enable signal /CE
1
, the output enable signal /OE, and the write enable signal /WE). The commands include, for example, a write command and a read command. The control decoder
20
provides a control signal (e.g., a write control signal wrz based on a write command or a read control signal rdz based on a read command), which is based on the decoded command to an activation pulse signal generator (ACTPGEN)
21
.
An external address signal Add is provided to an address transition detector (ATD)
24
via an input buffer
22
and a filter
23
. The address transition detector
24
detects the transition of an external address signal Add (e.g., the change in the lowermost bit A<
0
> of the external address signal Add) and generates a detection signal adrex.
The detection signals oerex, werex, cerex, adrex of the respective transition detectors
17
,
18
,
19
and the detection signal adrex of the address transition detector
24
are provided to an address transition detection signal (ATDS) generator (ATDGEN)
25
.
The ATDS generator
25
performs a logical operation on the detection signals oerex, werex, cerex, adrex and generates an activation signal atdpz based on the finally provided control signals /OE, /WE, /CE
1
and the external address signal Add. The activation signal atdpz is provided to an external active latch generator (EALGEN)
26
and a refresh controller (REFCTL)
27
.
The external active latch generator
26
generates a main signal mpealz, which activates a device based on the activation signal atdpz, and provides the main signal mpealz to the activation pulse signal generator
21
.
The activation pulse signal generator
21
generates a write signal wrtz, a read signal redz, and an activation pulse signal actpz based on the control signals wrz, rdz from the control decoder
20
and the main signal mpealz. The activation pulse signal actpz is provided to a row address generator (RASGEN)
28
. The activation pulse signal actpz is a signal that activates a row circuit, which controls word lines connected to a memory cell or a sense amp connected to bit lines, and a column circuit, which controls column gates connected to a data bus.
The refresh controller
27
is a so-called arbiter. The refresh controller
27
determines whether to select (give priority to) an internal refresh request (self-refresh request signal srtz) or an access request (activation signal atdpz) from an external device and generates a determination signal refz based on the determination. The determination signal refz is provided to the row address generator
28
.
The row address generator
28
generates a base signal rasz of the word line selection signal based on the determination signal refz and the activation pulse signal actpz. When the refresh controller
27
selects an internal refresh request, the word line corresponding to the refresh address is activated based on the base signal rasz. When the external access request is selected, the word line corresponding to the external address signal Add is activated based on the base signal rasz. The refresh address is generated by an address counter (not shown).
The operation of the DRAM
100
will now be discussed.
When Responding to an External Access Request
FIG. 2
is a waveform chart taken when responding to an access request from an external device.
When the chip enable signal /CE
1
goes low, the detection signals oerex, werex, cerex of the respective transition detectors
17
,
18
,
19
are output. Then, the ATDS generator
25
generates the activation signal atdpz. The main signal mpealz is generated based on the activation signal atdpz, and the activation pulse signal actpz is generated based on the main signal mpealz.
When responding to an external access request, the self-refresh request signal srtz is low. Thus, the determination signal refz remains unchanged (low level). The activation pulse signal generator
21
generates the activation pulse signal actpz and the write signal wrtz or the read signal redz based on the main signal mpealz from the external active latch generator
26
and the control signals wrz, rdz from the control decoder
20
. The write signal wrtz indicates the write mode, and the read signal redz indicates the read mode. The level of the control signals (/WE, /OE) determines which one of the write signal wrtz and the read signal redz is to be generated.
The row address generator
28
generates the base signal rasz, which selects the word lines, based on the activation pulse signal actpz. Since the circuit responding to the base signal rasz does not have a refresh request, the word line corresponding to the external address signal Add is selected.
When Selecting a Refresh Request
FIG. 3
is a waveform chart taken when the refresh request and the external access request overlap each other and the refresh request is selected.
When the refresh request is selected, the refresh controller
27
compares the activation signal atdpz and the internal refresh request signal srtz. If the refresh request signal srtz is earlier than the activation signal atdpz, the refresh controller
27
outputs the determination signal refz at a high level. Thus, the row address generator
28
gives priority to the internal refresh request and generates the base signal rasz to activate the word line c

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