Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-01-08
2004-01-20
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C036S039000, C036S052000, C365S189020, C365S230020, C365S230050, C365S230080
Reexamination Certificate
active
06681286
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a control chipset. More particularly, the present invention relates to a control chipset having dual-definition data pins. The dual-definition data pins are used to minimize overall wiring length of circuits from the control chipset to a memory module slot.
2. Description of Related Art
Synchronous dynamic random access memory (SDRAM) is often used in personal computers. SDRAM responds to the rising edge of a system clock cycle to carry out data a transmission operation. Another type of memory is double-data-rate dynamic random access memory (DDR DRAM). For a DDR DRAM, a data transmission operation is triggered at the rising edge and the falling edge of a system clock cycle. Hence, operating frequency of a DDR DRAM is almost double that of a SDRAM.
The operating modes of SDRAM and DDR DRAM differ in many other aspects, including: (1) SDRAM uses normal clock pulse signals while DDR DRAM uses differential clock signals; (2) SDRAM uses V
DD
=3.3V while DDR DRAM uses V
DD
=2.5V and V
DDQ
=2.5V; (3) SDRAM does not require a reference voltage, but DDR DRAM requires a reference voltage whose value is about ½ V
DDQ
; (4) SDRAM connects to a data bus that operates on CMOS logic while DDR DRAM connects to a data bus that operates on series-stub-terminated logic 2 (STTL
—
2); (5) there is no need for the SDRAM connected data bus connected to use a terminated voltage (V
TT
), but DDR DRAM connected data bus must use a terminated voltage (V
TT
) to absorb reflected waves; and (6) there is no need for the SDRAM connected data bus to use a pull-up resistor, but the DDR DRAM connected data bus must use a pull-up resistor. Nevertheless, a DDR DRAM is able to operate at a speed roughly double that of the SDRAM.
FIG. 1
is a block diagram showing the component layout of a conventional computer motherboard. The motherboard
100
includes a central processing unit (CPU)
140
, a control chipset
110
, a plurality of memory slots
120
for accommodating first type memory modules, a plurality of memory slots
130
for accommodating second type memory modules, a plurality of peripheral component interconnect (PCI) slots
150
an accelerated graphic port (AGP) slot
160
and a clock pulse generator
170
. Control chipset
110
has a plurality of data pins MD[
0
:
63
]. Each memory slot
120
has a plurality of data pins MD[
0
:
63
] for meshing with a 184-pin memory module. Each memory slot
130
has a plurality of data pins MD[
0
:
63
] for meshing with a 168-pin memory module. Each PCI slot
150
is used for accommodating a PCI interface card. AGP slot
160
is used for accommodating a window accelerator card. Clock pulse generator
170
is used for providing the much needed clock pulses to the memory modules.
As shown in
FIG. 1
, data pins MD[
0
:
63
] of control chipset
110
are directly connected to data pins MD[
0
:
63
] of memory slots
120
and data pins MD[
0
:
63
] of memory slots
130
respectively. The assignment of data pins MD[
0
:
63
] between memory slots
120
and memory slots
130
are very different. Hence, if similarly defined data pins of memory slot
120
and memory slot
130
are to be wired together, overall length of wires from data pins MD[
0
:
63
] of memory slot
120
to memory slot
130
may be excessive.
Table No. 1 illustrates the assignment of data pins MD[
0
:
63
] for memory slots
120
and memory slots
130
. As shown in Table No. 1, data pins MD
63
of memory slots
120
are connected to data pin MD
0
of memory slots
130
. Similarly, data pins MD
32
of memory slots
120
are connected to data pins MD
15
of memory slots
130
, and data pins MD
0
of memory slots
120
are connected to data pins MD
63
of memory slots
130
and so on. Only through this type of data pin assignments, wiring layout problems can be minimized.
TABLE 1
Assignment of data pins MD[0:63] for 184-pin memory module
slots and 168-pin memory module slots.
184
168
184
168
184
168
184
168
MD63
MD0
MD46
MD8
MD27
MD16
MD10
MD24
MD59
MD32
MD47
MD40
MD31
MD48
MD11
MD56
MD62
MD1
MD42
MD9
MD26
MD17
MD14
MD25
MD58
MD33
MD43
MD41
MD30
MD49
MD15
MD57
MD61
MD2
MD45
MD10
MD25
MD18
MD12
MD26
MD57
MD34
MD41
MD42
MD29
MD50
MD13
MD58
MD60
MD3
MD40
MD11
MD24
MD19
MD8
MD27
MD56
MD35
MD44
MD43
MD28
MD51
MD9
MD58
MD55
MD4
MD39
MD12
MD19
MD20
MD7
MD28
MD51
MD36
MD35
MD44
MD23
MD52
MD3
MD60
MD54
MD5
MD34
MD13
MD18
MD21
MD2
MD29
MD50
MD37
MD38
MD45
MD22
MD53
MD6
MD61
MD52
MD6
MD33
MD14
MD17
MD22
MD5
MD30
MD53
MD38
MD37
MD46
MD21
MD54
MD1
MD62
MD48
MD7
MD32
MD15
MD20
MD23
MD4
MD31
MD49
MD39
MD36
MD47
MD16
MD55
MD0
MD63
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a control chipset having dual-definition data pins for reducing the wiring layout to memory module slots. The control chipset of this invention is designed according to the data pin assignment of Table No. 1 but each data pin is a dual-definition pin. For example, data pins MD
63
are defined to be MD
63
/MD
0
, data pins MD
59
are defined to be MD
59
/MD
32
, data pins MD
62
are defined to be MD
62
/MD
1
, . . . , and data pins MD
0
are defined to be MD
0
/MD
63
. Hence, data pins MD[
0
:
63
] of first type memory modules can be linked closely with data pins MD[
0
:
63
] of second type memory modules. Together with a control chipset capable of outputting data to various data pins MD[
0
:
63
], problem of having to use excessive wires to link up data pins MD[
0
:
63
] between a first and a second type memory slot is greatly minimized.
When first type memory modules are in first type memory slots, the control chipset outputs data to the data pins MD
63
, MD
59
, MD
62
, . . . , MD
0
, a configuration for operating first type memory module. On the other hand, when second type memory modules are in second type memory slots, the control chipset outputs data to data pins MD
0
, MD
32
, MD
1
, . . . , MD
63
, a configuration for operating second type memory module.
The control chipset of this invention has n data pins with each data pin serving dual functions. In other words, the jth data pin is defined as the ath pin of a first sequence and the bth pin of a second sequence while the kth data pin is defined as the bth pin of the first sequence and the cth pin of the second sequence. The control chipset includes a first first-in first-out (FIFO) memory, a multiplexing device, a second first-in first-out (FIFO) memory and a de-multiplexing device. The first FIFO memory has at least n pin output terminal for temporarily holding output data. The multiplexing device is connected to the first FIFO memory and the n data pins of the control chipset. The multiplexing device has n first type input terminals, n second type input terminals, n output terminals and a selective input terminal. Whether the xth output terminal of the n output terminals is equal to the xth input terminal of the first type input terminals or the xth input terminal of the second type input terminals depends on the selective input terminal of the multiplexing device. The xth output terminal is connected to the xth data pin of a plurality of data pins. The bth pin output terminal of the first FIFO memory is connected the jth input terminal of the second type input terminal and the kth input terminal of the first type input terminal. The second FIFO memory has at least n pin input terminal for temporarily holding input data. The de-multiplexing device is connected to the n data pins of the control chipset. The de-multiplexing device has n first type output terminals, n second type output terminals, n input terminals and a selective input terminal. Whether the xth input terminal of the n input terminals is equal to the xth output terminal of the first type output terminals or the xth output terminal of the second type output terminals depends on the selective input terminal of the de-multiplexing device. The xt
Chang Nai-Shung
Yu Chia-Hsing
J. C. Patents
Shin Christopher B.
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