Control chip with multiple-layer defer queue

Details Control chip with multiple-layer defer queue Control chip with multiple-layer defer queue

2005-05-24

2005-05-24

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S169000, C710S006000, C710S025000, C710S039000, C710S058000, C710S112000, C710S306000, C710S310000, C710S313000

Reexamination Certificate

active

06898684

ABSTRACT:
A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

REFERENCES:
patent: 5991819 (1999-11-01), Young
patent: 6073190 (2000-06-01), Rooney
patent: 6247102 (2001-06-01), Chin et al.

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